One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge.
A detailed description of VADL can be found on arXiv
VADL has been released as open source (OpenVADL). The implementation language of VADL is JAVA 25 or higher. To improve the performance and functionality of the system it is necessary to optimize the new parser, optimize the instruction decoder, improve the assembler and linker generator, add support for GCC, add support for superscaler micro architectures, add floating point support, add automatic test generation, add support for tensor instructions in the compiler, simulator and hardware generator and improve the documentation generation.
Bachelor projects must be doable in 250 to 300 hours. Therefore, only a small subset of the topics are available. Possible small topics are rewrite (parts of) the generic compiler infrastructure, evaluate the compiler optimizations to improve the generated compiler, extend the QEMU generator to support delayed branches / register writes and test it with MIPS IV, improve user mode emulation for the generated QEMU, add features to the hardware generation (e.g. better instruction fetch, improved branch prediction, load / store queues) specify additional architectures in VADL, develop simple and more advanced test generators, optimize the HTML dump of the VIAM (VADL Intermediate Architecture Model) extend testing of all developed OpenVADL components.