Master and Bachelor Theses

LLVM Compiler Generator in OpenVADL

Kevin Per

Generation of Assemblers and Linkers in OpenVADL

Benjamin Kasper

Instruction Set Simulation of VLIW Architectures in VADL

Niklas Mischkulnig

Atomic Instruction and Cache-Support for VADL

Simon Himmelbauer

Efficient parsing of OpenVADL

Michael Nestler

Debugging Interface for VADL

Simon Josef Kreuzpointner

Optimized processor simulation with VADL

Hristo Mihaylov

Flexible generation of low-level developer tools with VADL

Tobias Schwarzinger

Compiler backend generation using the VADL processor description language

Alexander Graf

Cycle-Accurate simulator generator for the VADL processor description language

Hermann Schützenhöfer