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Dynamic Binary Translation for Generation of Cycle Accurate Architecture Simulators Andreas Krall Presentation at Emerging Uses and Paradigms for Dynamic Binary Translation Germany, Schloss Dagstuhl, October, 2008 |
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Generalized Instruction Selection using SSA-Graphs Dietmar Ebner, Florian Brandner, Bernhard Scholz, Andreas Krall, Peter Wiedermann and Albrecht Kadlec ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES) Tucson, June, 2008 |
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Compiler Optimizations for Processors with SIMD Instructions Ivan Pryanishnikov, Andreas Krall, Nigel Horspool Software - Practice and Experience, Vol. 37, 93-113, 2007 |
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Compiler Generation from Structural Architecture Descriptions Florian Brandner, Dietmar Ebner, Andreas Krall International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Salzburg, October, 2007 |
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Leveraging Predicated Execution for Multimedia Processing Dietmar Ebner, Florian Brandner, Andreas Krall Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia) Salzburg, October, 2007 |
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Instruction Set Encoding Optimization for Code Size Reduction Michael Med, Andreas Krall Proceedings of 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007) Samos, Greece, July, 2007 |
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Short Presentation: Static Verification of Global Heap References in Java Native Libraries Andreas Krall, Christian Thalinger, Dietmar Ebner and Florian Brandner In Proceedings of the third workshop on Semantics, Program Analysis, and Computing Environments for memory management. |
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Superinstructions and Replication in the Cacao JVM Interpreter M. Anton Ertl, Christian Thalinger and Andreas Krall In Proceedings of the 4th International Conference in Central Europe on .NET Technologies. |
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Effective Compiler Generation by Architecture Description Stefan Farfeleder, Andreas Krall, Edwin Steiner and Florian Brandner In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems, Ottawa, June, 2006. |
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Control flow graph reconstruction for assembly language programs with delayed instructions Nerina Bermudo and Nigel Horspool and Andreas Krall In Proceedings of the fifth International Workshop on Source Code Analysis and Manipulation (SCAM'05), pages 107-116, Budapest, 2005 |
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Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures Andreas Krall and Stefan Farfeleder and Nigel Horspool In Proceedings of SAMOS05, Pages 222-231, 2005 |
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xDSPcore: A Compiler-Based Configureable Digital Signal Processor Andreas Krall and Ulrich Hirnschrott and Christian Panis and Ivan Pryanishnikov IEEE Micro, Volume 24, Pages 67-78, 2004 |
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A Scalable DSP Core for SoC Applications Christian Panis and Ulrich Hirnschrott and Andreas Krall and Stefan Farfeleder and Gunther Laure and Wolfgang Lazian and Jari Nurmi In Proceedings of the International Symposium on System-on Chip (SOC 2004), Tampere, 2004 |
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DSPxPlore - Design Space Exploration Methodology for an Embedded DSP Core Christian Panis and Ulrich Hirnschrott and Gunther Laure and Wolfgang Lazian and Jari Nurmi In Proceedings of the Symposium on Applied Computing, Nicosia, 2004 |
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FSEL - Selective Predicated Execution for a Configurable DSP Core Christian Panis and Ulrich Hirnschrott and Andreas Krall and Gunther Laure and Wolfgang Lazian and Jari Nurmi In Proceedings of the Annual Symposium on VLSI, Pages 317-320, Lafayette, Luisiana, 2004 |
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Optimizing and Porting the CACAO JVM Christian Thalinger Master's Thesis, Vienna University of Technology, 2004 |
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A fast and accurate framework to analyze and optimize cache memory behavior Xavier Vera and Nerina Bermudo and Josep Llosa and Antonio Gonzalez In ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 26, Issue 2, Pages 263-300, 2004 |
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Exploiting Distributed-Memory and Shared-Memory Parallelism on
Clusters of SMPs with Data Parallel Programs Siegfried Benkner and Viera Sipkova International Journal of Parallel Programming, Volume 31, Pages 3 - 19, February 2003 |
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Pointer Alignment Analysis for Processors with SIMD Instruction Ivan Pryanishnikov, Andreas Krall and R.Nigel Horspool In Proceedings of the 5th Workshop on Media and Streaming Processors held in conjunction with MICRO-36 (MSP'03), San Diego, CA, December 1, 2003 |
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Efficient variable allocation to dual memory banks of DSPs Viera Sipkova In Proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems (SCOPES'03), Vienna, Austria, September 2003, Springer Verlag (LNCS 2826), pp. 359-372. |
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VLIW operation refinement for reducing energy consumption Ulrich Hirnschrott and Andreas Krall In Proceedings of the International Symposium on System-On-Chip (SOC'03), IEEE 2003. |
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DSPxPlore-design space exploration for a configurable DSP core Ch. Panis, G. Laure, W. Lazian, H. Grünbacher, A. Krall, J. Nurmi In Asim Smailagic, editor, International Signal Processing Conference, Dallas, April 2003. GSPx. |
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Graph coloring vs. optimal register allocation for optimizing compilers Ulrich Hirnschrott, Andreas Krall and Bernhard Scholz In Proceedings of the Joint Modular Language Conference (JMLC) 2003, LNCS, Klagenfurt, August 2003. |
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Register liveness analysis for optimizing dynamic binary translation Mark Probst, Andreas Krall and Bernhard Scholz In Proceedings of the Working Conference on Reverse Engineering (WCRE'02), October/November 2002, Richmond, Virginia, USA. |
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Dynamic binary translation Mark Probst In UKUUG Linux Developer's Conference, 2002. |
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