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7th International Workshop on
Software and Compilers for Embedded Systems

Final Workshop Program

Wednesday, 09/24/2003

Thursday, 09/25/2003

Friday, 09/26/2003

09:00 - 10:30 code size reduction (Nigel Horspool)
Qin Zhao, Bart Mesman, Henk Corporaal: Limited Address Range Architecture for Reducing Code Size in Embedded Processors (slides)
Warren Cheung, William Evans, Jeremy Moses: Predicated Instructions for Code Compaction
Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson: Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation (slides)
09:00 - 10:00 (Shuvra S. Bhattacharyya)
Jim Dehnert (Transmeta), Invited talk: The Transmeta Crusoe: VLIW Embedded in CISC (slides (7704 KByte))
09:00 - 10:30 analysis and profiling (Andreas Krall)
Raimund Kirner, Peter Puschner: Transformation of Meta-Information by Abstract Interpretation
R.Stahl, R.Pasko, L.Rijnders, D.Verkest, S.Vernalde, R.Lauwereins, F.Catthor: Performance Analysis for Identification of (Sub)task-Level Parallelism in Java (slides)
Kevin Casey, David Gregg, Anton Ertl: Towards Superinstructions for Java Interpreters
10:30 - 12:30 system design (Uwe Assmann)
Arshad Jhumka, Neeraj Suri: A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs (slides)
Hiroo Ishikawa, Tatsuo Nakajima: A Case Study on a Component-based System and its Configuration
Kirk Schloegel, David Oglesby, Eric Engstrom, Devesh Bhatt: Composable Code Generation for Model-based Development
Ioannis Charitakis, Dionisios Pnevmatikatos, Evangelos Markatos: S2I: A Tool for Automatic Rule Match Compilation for the IXP Network Processor (slides)
11:00 - 12:30 code selection (Anton Ertl)
Erik Eckstein, Oliver König, Bernhard Scholz: Code Instruction Selection based on SSA-Graphs
Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Tkeuchi, Keishi Sakanushi, Masaharu Imai: A Code Selection Method for SIMD Processors with PACK Instructions (slides)
Björn Decker, Daniel Kästner: Reconstructing Control Flow from Predicated Assembly Code (slides)
11:00 - 13:00 memory and cache optimizations (Peter Marwedel)
Ming-Yung Ko, Shuvra S. Bhattacharyya: Data Partitioning for DSP Software Synthesis
Viera Sipkova: Efficient Variable Allocation to Dual Memory Banks of DSPs (slides)
Diego Andrade, Basilio B. Fraguela, Ramon Doallo: Cache Behavior Modeling of Codes with Data-Dependent Conditionals (slides)
Marco Garatti: FICO: A Fast Instruction Cache Optimizer (slides)
14:00 - 15:30 loop optimizations (David Gregg)
Stefaan Himpe, Francky Catthor, Geert Deconinck: Control Flow Analysis for Recursion Removal (slides)
Litong Song, Krishna Kavi: An Unfolding-Based Loop Optimization Technique
Gang-Ryung Uh: Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer (slides)
14:00 - 15:00 register allocation (Jens Knoop)
Johan Runeson, Sven-Olof Nyström: Retargetable Graph-Coloring Register Allocation for Irregular Architectures (slides)
Dae-Hwan Kim, Hyuk-Jae Lee: Fine-Grain Register Allocation Based on a Global Spill Costs Analysis (slides)
15:30 - 16:30 offset assignment (Reinhard Leupers)
Sarvani V.V.N.S., R.Govindarajan: Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers: Improving Offset Assignment through Simultaneous Variable Coalescing (slides)
16:00 - 17:00 automatic retargeting (Hans van Someren)
Yunheung Paek, Minwook Ahn, Soonho Lee: Case Studies on Automatic Extraction of Target-specific Architectural Parameters in Complex Code Generation (slides)
O.Wahlen, M.Hohenauer, G.Braun, R.Leupers, G.Ascheid, H.Meyr, X.Nie: Extraction of Efficient Instruction Schedulers from Cycle-true Processor Models (slides)
17:15 - 18:00 discussion (Peter Marwedel) (slides) 17:00 - 17:45 discussion (Jim Dehnert)
Workshop dinner at Palais Schwarzenberg