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version 1.5, 2009/06/26 10:31:16 version 1.8, 2009/06/28 16:26:25
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 \title{\bf PP \emph{Compilation Techniques for Robust Embedded Systems}}  \title{\bf PP \emph{Compilation Techniques for Robust Embedded Systems}}
   
 \author{{\sc Ulrich Schmid}\\  \author{{\sc Andreas Krall and Jens Knoop}\\
 s@ecs.tuwien.ac.at  \{andi,knoop\}@complang.tuwien.ac.at
 }  }
   
 \bibliographystyle{unsrt}  \bibliographystyle{unsrt}
Line 70  in the Handbook of Signal Processing sys Line 70  in the Handbook of Signal Processing sys
 instruction set simulator with modelling of energy consumtion is Wattch  instruction set simulator with modelling of energy consumtion is Wattch
 \cite{BrooksTiwariMartonosi00}.  \cite{BrooksTiwariMartonosi00}.
   
 Compiler Verification \cite{Hoare,1328444,1314860}  Compiler Verification
   
    \cite{Hoare03}
    \cite{TristanLeroy09}
    \cite{TristanLeroy08}
    \cite{Kundu+09}
    \cite{Necula00} 
    \cite{ZaksPnueli08}
    \cite{Pnueli98a}
    \cite{Pnueli98b}
    \cite{GlesnerGoosZimmeermann04}
    \cite{GoosZimmermann00}
    \cite{BlechPoetzsch07}
   
 WCET \cite{}  WCET \cite{}
   
Line 121  Techniques for reducing or eliminating t Line 133  Techniques for reducing or eliminating t
 %to also describe and (coarsely) quantify the resources (staff, cost of   %to also describe and (coarsely) quantify the resources (staff, cost of 
 %special equipment) required for this work in a table. (20-30 lines)}  %special equipment) required for this work in a table. (20-30 lines)}
   
 The project is divided into three work packages.  Compilation techniques for robust embedded systems comprise different areas.
   Therefore, the project is divided into three work packages: compilation and
   simulation techniques for reliabiltiy, verified compilation and worst case
   execution time analysis.
   
 \paragraph*{WP1 - Compilation and Simulation Techniques for Reliability}  \paragraph*{WP1 - Compilation and Simulation Techniques for Reliability}
   
 (1) Specification and efficient simulation of reliable processors  In previous work we have developed a processor description language
 (partial redundancy, ECC, lockstep etc) and compiler optimizations to  with a very concise semantics from where we automatically generate
 exploit/balance reliabiliy features. Connection with CESAR NN1  optimized compilers \cite{BrEbKr07} and high efficient instruction set
   simulators \cite{BrFeKrRi09}. This environment we use as testbed for
   our compiler optimizations for embedded processors
   \cite{EbBrSchKrWiKa08,PrKrHo06,MeKr07}. We will extend this
   environment to do research on compilation and simulation techniques to
   enhance the reliability of processor/memory systems by mixed
   hardware/software and pure software techniques. 
   
 \begin{itemize}  \begin{itemize}
 \item Specification method to specify an energy consumption model in  \item Specification method to specify an energy consumption model in
Line 137  exploit/balance reliabiliy features. Con Line 158  exploit/balance reliabiliy features. Con
 \item Specification method for fault injection and fault checking in  \item Specification method for fault injection and fault checking in
       the processor specification        the processor specification
 \item Generation of optimized instruction set simulators from the  \item Generation of optimized instruction set simulators from the
       processor specification        extended processor specification
 \item Generation of optimizing compilers from the processor specification  \item Generation of optimizing compilers from the extended processor
         specification
 \item Research into new compiler optimizations to increase reliability by  \item Research into new compiler optimizations to increase reliability by
       pure software solutions, mixed hardware/software solutions and        pure software solutions, mixed hardware/software solutions and
       balancing performance, code space, reliability and energy consumption        balancing performance, code space, reliability and energy consumption
Line 148  exploit/balance reliabiliy features. Con Line 170  exploit/balance reliabiliy features. Con
   
 \paragraph*{WP2 - Verified Compilation}  \paragraph*{WP2 - Verified Compilation}
   
 translation verification, specification of semantics of IRs solving  Suitable semantics are necessary which support efficient translation
 subproblems.  validation or support easy verification of a compiler. We will research
   into different semantics and into mappings between the semantics of our
   processor description language \cite{BrEbKr07} and a compiler backend
   semantics, intermediate representation semantics (compatible to LLVM) and
   source language semantics. The main research will be on verification and
   translation validation for all kinds of compiler optimizations.
   
   \begin{itemize}
   \item Evaluate different semantics regarding suitability for compiler
         verification and translation validation, eventually develop new
         semantics
   \item Develop a translator for an automatic mapping from our processor
         description language into verification semantics
   \item Develop a validation system from the intermediate representation
         (LLVM) to the processor semantics
   \item Develop a validation system from the source language (C) to the
         intermediate representation (LLVM)
   \item Research into verification and translation validation for different
         frontend and backend optimizations
   \end{itemize}
   
 \paragraph*{WP3 - Worst Case Ececution Time Analysis}  \paragraph*{WP3 - Worst Case Ececution Time Analysis}
   
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