Diff for /res/PP-compiler.tex between versions 1.1 and 1.2

version 1.1, 2009/06/09 09:59:25 version 1.2, 2009/06/22 14:23:22
Line 28  s@ecs.tuwien.ac.at Line 28  s@ecs.tuwien.ac.at
 \begin{document}  \begin{document}
 \maketitle  \maketitle
   
 PP leader: \emph{Jens Knoop}  PP leader: \emph{Jens Knoop and Andreas Krall}
   
 Associated researchers: \emph{Andreas Krall}  Associated researchers: \emph{}
   
   
   
Line 45  concurrency and reliability. Line 45  concurrency and reliability.
 \subsubsection*{State of the art and related work:}   \subsubsection*{State of the art and related work:} 
 %\emph{Briefly describe the scientific state of the art (20-30 lines)}  %\emph{Briefly describe the scientific state of the art (20-30 lines)}
   
 Compiler Verification \cite{Hoare,1328444,1314860}  %Compilation Techniques for Reliability
   
   Because of the exponential increase of the number of transistors and
   the continuing decrease of the feature sizes of current processors
   soft errors mainly caused by energetic particles are becoming an
   important design issue for robust embedded systems. Blome et
   al.~\cite{Blome+06} observed that a majority of faults that affect the
   architectural state of a processor come from the register file. Lee
   and Shrivastava and proposed different solutions to cope with this
   problem. The first assigns variables depending on their lifetime to
   either the ECC protected or the unprotected part of a register file to
   balance energy consumption and reliability \cite{LeeShrivastava09a}.
   The second spills registers to ECC protected memory if the register
   contents are not used for a long period \cite{LeeShrivastava09c}.
   
 Reliability \cite{LeeShrivastava09}  %ADL and Instruction Set Simulators \cite{MishraDutt08}
   
 ADL \cite{MishraDutt08}  Compiler Verification \cite{Hoare,1328444,1314860}
   
 WCET \cite{}  WCET \cite{}
   
Line 102  Techniques for reducing or eliminating t Line 115  Techniques for reducing or eliminating t
   
   
   
 (1) WCET NN!  (1) Specification and efficient simulation of reliable processors (partial redundancy,
   
 (2) Specification and efficient simulation of reliable processors (partial redundancy,  
 ECC, lockstep etc) and compiler optimizations to exploit/balance reliabiliy features.  ECC, lockstep etc) and compiler optimizations to exploit/balance reliabiliy features.
 Connection with CESAR NN2  Connection with CESAR NN1
   
 (3) translation verification, specification of semantics of IRs solving  (2) translation verification, specification of semantics of IRs solving
 subproblems. NN1 + NN2  subproblems. NN1 + NN2
   
   (3) WCET NN3
   
   
 \begin{tabular}{llll}  \begin{tabular}{llll}
 \hline  \hline
 {\bf Pos} & {\bf Type} & {\bf Description}        & {\bf Duration} \\  {\bf Pos} & {\bf Type} & {\bf Description}    & {\bf Duration} \\
 NN1 & PostDoc & WCET                              & 4 years \\  NN1 & PhD & reliable compilation / simulation & 4 years \\
 NN2 & PostDoc & reliable compilation / simulation & 4 years \\  NN2 & PhD & compiler verificationi            & 4 years \\
   NN3 & PhD & WCET                              & 4 years \\
 \hline  \hline
 \end{tabular}  \end{tabular}
   
Line 161  Techniques for adjusting and decompiling Line 175  Techniques for adjusting and decompiling
 %describe briefly the topic and nature  of such a collaboration. (5-10  %describe briefly the topic and nature  of such a collaboration. (5-10
 %lines)}  %lines)}
   
 To be done.  Aviral Shrivastava, Arizona State University, Tempe, AZ, USA
   
   Wolf Zimmermann, Universit\"at Halle, Halle, Germany
   
 \begin{comment}  \begin{comment}
 %Bitte hier die Bibtex-Entries  einfuellen, z.B.,  %Bitte hier die Bibtex-Entries  einfuellen, z.B.,

Removed from v.1.1  
changed lines
  Added in v.1.2


FreeBSD-CVSweb <freebsd-cvsweb@FreeBSD.org>