version 1.1, 2009/06/09 09:59:25
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version 1.2, 2009/06/22 14:23:22
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Line 28 s@ecs.tuwien.ac.at
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Line 28 s@ecs.tuwien.ac.at
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\begin{document} |
\begin{document} |
\maketitle |
\maketitle |
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PP leader: \emph{Jens Knoop} |
PP leader: \emph{Jens Knoop and Andreas Krall} |
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Associated researchers: \emph{Andreas Krall} |
Associated researchers: \emph{} |
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Line 45 concurrency and reliability.
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Line 45 concurrency and reliability.
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\subsubsection*{State of the art and related work:} |
\subsubsection*{State of the art and related work:} |
%\emph{Briefly describe the scientific state of the art (20-30 lines)} |
%\emph{Briefly describe the scientific state of the art (20-30 lines)} |
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Compiler Verification \cite{Hoare,1328444,1314860} |
%Compilation Techniques for Reliability |
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Because of the exponential increase of the number of transistors and |
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the continuing decrease of the feature sizes of current processors |
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soft errors mainly caused by energetic particles are becoming an |
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important design issue for robust embedded systems. Blome et |
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al.~\cite{Blome+06} observed that a majority of faults that affect the |
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architectural state of a processor come from the register file. Lee |
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and Shrivastava and proposed different solutions to cope with this |
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problem. The first assigns variables depending on their lifetime to |
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either the ECC protected or the unprotected part of a register file to |
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balance energy consumption and reliability \cite{LeeShrivastava09a}. |
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The second spills registers to ECC protected memory if the register |
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contents are not used for a long period \cite{LeeShrivastava09c}. |
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Reliability \cite{LeeShrivastava09} |
%ADL and Instruction Set Simulators \cite{MishraDutt08} |
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ADL \cite{MishraDutt08} |
Compiler Verification \cite{Hoare,1328444,1314860} |
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WCET \cite{} |
WCET \cite{} |
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Line 102 Techniques for reducing or eliminating t
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Line 115 Techniques for reducing or eliminating t
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(1) WCET NN! |
(1) Specification and efficient simulation of reliable processors (partial redundancy, |
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(2) Specification and efficient simulation of reliable processors (partial redundancy, |
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ECC, lockstep etc) and compiler optimizations to exploit/balance reliabiliy features. |
ECC, lockstep etc) and compiler optimizations to exploit/balance reliabiliy features. |
Connection with CESAR NN2 |
Connection with CESAR NN1 |
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(3) translation verification, specification of semantics of IRs solving |
(2) translation verification, specification of semantics of IRs solving |
subproblems. NN1 + NN2 |
subproblems. NN1 + NN2 |
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(3) WCET NN3 |
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\begin{tabular}{llll} |
\begin{tabular}{llll} |
\hline |
\hline |
{\bf Pos} & {\bf Type} & {\bf Description} & {\bf Duration} \\ |
{\bf Pos} & {\bf Type} & {\bf Description} & {\bf Duration} \\ |
NN1 & PostDoc & WCET & 4 years \\ |
NN1 & PhD & reliable compilation / simulation & 4 years \\ |
NN2 & PostDoc & reliable compilation / simulation & 4 years \\ |
NN2 & PhD & compiler verificationi & 4 years \\ |
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NN3 & PhD & WCET & 4 years \\ |
\hline |
\hline |
\end{tabular} |
\end{tabular} |
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Line 161 Techniques for adjusting and decompiling
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Line 175 Techniques for adjusting and decompiling
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%describe briefly the topic and nature of such a collaboration. (5-10 |
%describe briefly the topic and nature of such a collaboration. (5-10 |
%lines)} |
%lines)} |
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To be done. |
Aviral Shrivastava, Arizona State University, Tempe, AZ, USA |
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Wolf Zimmermann, Universit\"at Halle, Halle, Germany |
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\begin{comment} |
\begin{comment} |
%Bitte hier die Bibtex-Entries einfuellen, z.B., |
%Bitte hier die Bibtex-Entries einfuellen, z.B., |