--- gforth/prim 2005/01/26 21:24:15 1.163 +++ gforth/prim 2005/01/29 13:31:51 1.168 @@ -249,7 +249,6 @@ execute ( xt -- ) core #ifndef NO_IP ip=IP; #endif -/* IF_spTOS(spTOS = sp[0]); /* inst_tail would produce a NEXT_P1 */ SUPER_END; VM_JUMP(EXEC1(xt)); @@ -259,7 +258,6 @@ perform ( a_addr -- ) gforth #ifndef NO_IP ip=IP; #endif -/* IF_spTOS(spTOS = sp[0]); /* inst_tail would produce a NEXT_P1 */ SUPER_END; VM_JUMP(EXEC1(*(Xt *)a_addr)); : @@ -521,10 +519,8 @@ if (nstart == nlimit) { JUMP(a_target); #else SET_IP((Xt *)a_target); - INST_TAIL; NEXT_P2; #endif } -SUPER_CONTINUE; : 2dup = IF r> swap rot >r >r @@ -544,10 +540,8 @@ if (nstart >= nlimit) { JUMP(a_target); #else SET_IP((Xt *)a_target); - INST_TAIL; NEXT_P2; #endif } -SUPER_CONTINUE; : swap 2dup r> swap >r swap >r @@ -567,10 +561,8 @@ if (ustart >= ulimit) { JUMP(a_target); #else SET_IP((Xt *)a_target); -INST_TAIL; NEXT_P2; #endif } -SUPER_CONTINUE; : swap 2dup r> swap >r swap >r @@ -590,10 +582,8 @@ if (nstart <= nlimit) { JUMP(a_target); #else SET_IP((Xt *)a_target); -INST_TAIL; NEXT_P2; #endif } -SUPER_CONTINUE; : swap 2dup r> swap >r swap >r @@ -613,10 +603,8 @@ if (ustart <= ulimit) { JUMP(a_target); #else SET_IP((Xt *)a_target); -INST_TAIL; NEXT_P2; #endif } -SUPER_CONTINUE; : swap 2dup r> swap >r swap >r @@ -869,7 +857,7 @@ DCell d = (DCell)n1 * (DCell)n2; #endif #ifdef BUGGY_LL_DIV DCell r = fmdiv(d,n3); -n4=DHI(r); +n4=DLO(r); #else /* assumes that the processor uses either floored or symmetric division */ n4 = d/n3; @@ -898,10 +886,25 @@ n2 = n1>>1; fm/mod ( d1 n1 -- n2 n3 ) core f_m_slash_mod ""Floored division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, @i{n1}>@i{n2}>=0 or 0>=@i{n2}>@i{n1}."" #ifdef BUGGY_LL_DIV +#ifdef ASM_SM_SLASH_REM +ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); +if ((d1.hi<0) != (n1<0) && n2!=0) { + n3--; + n2+=n1; +} +#else /* !defined(ASM_SM_SLASH_REM) */ DCell r = fmdiv(d1,n1); n2=DHI(r); n3=DLO(r); +#endif /* !defined(ASM_SM_SLASH_REM) */ #else +#ifdef ASM_SM_SLASH_REM4 +ASM_SM_SLASH_REM4(d1, n1, n2, n3); +if ((d1<0) != (n1<0) && n2!=0) { + n3--; + n2+=n1; +} +#else /* !defined(ASM_SM_SLASH_REM4) */ /* assumes that the processor uses either floored or symmetric division */ n3 = d1/n1; n2 = d1%n1; @@ -910,6 +913,7 @@ if (1%-3>0 && (d1<0) != (n1<0) && n2!=0) n3--; n2+=n1; } +#endif /* !defined(ASM_SM_SLASH_REM4) */ #endif : dup >r dup 0< IF negate >r dnegate r> THEN @@ -920,10 +924,17 @@ if (1%-3>0 && (d1<0) != (n1<0) && n2!=0) sm/rem ( d1 n1 -- n2 n3 ) core s_m_slash_rem ""Symmetric division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, sign(@i{n2})=sign(@i{d1}) or 0."" #ifdef BUGGY_LL_DIV +#ifdef ASM_SM_SLASH_REM +ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); +#else /* !defined(ASM_SM_SLASH_REM) */ DCell r = smdiv(d1,n1); n2=DHI(r); n3=DLO(r); +#endif /* !defined(ASM_SM_SLASH_REM) */ #else +#ifdef ASM_SM_SLASH_REM4 +ASM_SM_SLASH_REM4(d1, n1, n2, n3); +#else /* !defined(ASM_SM_SLASH_REM4) */ /* assumes that the processor uses either floored or symmetric division */ n3 = d1/n1; n2 = d1%n1; @@ -932,6 +943,7 @@ if (1%-3<0 && (d1<0) != (n1<0) && n2!=0) n3++; n2-=n1; } +#endif /* !defined(ASM_SM_SLASH_REM4) */ #endif : over >r dup >r abs -rot @@ -969,12 +981,20 @@ ud = (UDCell)u1 * (UDCell)u2; um/mod ( ud u1 -- u2 u3 ) core u_m_slash_mod ""ud=u3*u1+u2, u1>u2>=0"" #ifdef BUGGY_LL_DIV +#ifdef ASM_UM_SLASH_MOD +ASM_UM_SLASH_MOD(ud.lo, ud.hi, u1, u2, u3); +#else /* !defined(ASM_UM_SLASH_MOD) */ UDCell r = umdiv(ud,u1); u2=DHI(r); u3=DLO(r); +#endif /* !defined(ASM_UM_SLASH_MOD) */ #else +#ifdef ASM_UM_SLASH_MOD4 +ASM_UM_SLASH_MOD4(ud, u1, u2, u3); +#else /* !defined(ASM_UM_SLASH_MOD4) */ u3 = ud/u1; u2 = ud%u1; +#endif /* !defined(ASM_UM_SLASH_MOD4) */ #endif : 0 swap [ 8 cells 1 + ] literal 0