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1.1 anton 1: /* taken from gcc-4.1.1 */
2: /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
1.4 ! anton 3: Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2004, 2005,2006,2007 Free Software Foundation, Inc.
1.1 anton 4:
5: This definition file is free software; you can redistribute it
6: and/or modify it under the terms of the GNU General Public
7: License as published by the Free Software Foundation; either
8: version 2, or (at your option) any later version.
9:
10: This definition file is distributed in the hope that it will be
11: useful, but WITHOUT ANY WARRANTY; without even the implied
12: warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13: See the GNU General Public License for more details.
14:
15: You should have received a copy of the GNU General Public License
16: along with this program; if not, write to the Free Software
17: Foundation, Inc., 51 Franklin Street, Fifth Floor,
18: Boston, MA 02110-1301, USA. */
19:
20: /* You have to define the following before including this file:
21:
22: UWtype -- An unsigned type, default type for operations (typically a "word")
23: UHWtype -- An unsigned type, at least half the size of UWtype.
24: UDWtype -- An unsigned type, at least twice as large a UWtype
25: W_TYPE_SIZE -- size in bits of UWtype
26:
27: UQItype -- Unsigned 8 bit type.
28: SItype, USItype -- Signed and unsigned 32 bit types.
29: DItype, UDItype -- Signed and unsigned 64 bit types.
30:
31: On a 32 bit machine UWtype should typically be USItype;
32: on a 64 bit machine, UWtype should typically be UDItype. */
33:
34: #define __BITS4 (W_TYPE_SIZE / 4)
35: #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
36: #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
37: #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
38:
39: #ifndef W_TYPE_SIZE
40: #define W_TYPE_SIZE 32
41: #define UWtype USItype
42: #define UHWtype USItype
43: #define UDWtype UDItype
44: #endif
45:
46: extern const UQItype __clz_tab[256];
47:
48: /* Define auxiliary asm macros.
49:
50: 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
51: UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
52: word product in HIGH_PROD and LOW_PROD.
53:
54: 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
55: UDWtype product. This is just a variant of umul_ppmm.
56:
57: 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
58: denominator) divides a UDWtype, composed by the UWtype integers
59: HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
60: in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
61: than DENOMINATOR for correct operation. If, in addition, the most
62: significant bit of DENOMINATOR must be 1, then the pre-processor symbol
63: UDIV_NEEDS_NORMALIZATION is defined to 1.
64:
65: 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
66: denominator). Like udiv_qrnnd but the numbers are signed. The quotient
67: is rounded towards 0.
68:
69: 5) count_leading_zeros(count, x) counts the number of zero-bits from the
70: msb to the first nonzero bit in the UWtype X. This is the number of
71: steps X needs to be shifted left to set the msb. Undefined for X == 0,
72: unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
73:
74: 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
75: from the least significant end.
76:
77: 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
78: high_addend_2, low_addend_2) adds two UWtype integers, composed by
79: HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
80: respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
81: (i.e. carry out) is not stored anywhere, and is lost.
82:
83: 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
84: high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
85: composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
86: LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
87: and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
88: and is lost.
89:
90: If any of these macros are left undefined for a particular CPU,
91: C macros are used. */
92:
93: /* The CPUs come in alphabetical order below.
94:
95: Please add support for more CPUs here, or improve the current support
96: for the CPUs below!
97: (E.g. WE32100, IBM360.) */
98:
99: #if defined (__GNUC__) && !defined (NO_ASM)
100:
101: /* We sometimes need to clobber "cc" with gcc2, but that would not be
102: understood by gcc1. Use cpp to avoid major code duplication. */
103: #if __GNUC__ < 2
104: #define __CLOBBER_CC
105: #define __AND_CLOBBER_CC
106: #else /* __GNUC__ >= 2 */
107: #define __CLOBBER_CC : "cc"
108: #define __AND_CLOBBER_CC , "cc"
109: #endif /* __GNUC__ < 2 */
110:
1.3 anton 111: #if defined (__alpha) && W_TYPE_SIZE == 64 && __GNUC__ >= 3
1.1 anton 112: #define umul_ppmm(ph, pl, m0, m1) \
113: do { \
114: UDItype __m0 = (m0), __m1 = (m1); \
115: (ph) = __builtin_alpha_umulh (__m0, __m1); \
116: (pl) = __m0 * __m1; \
117: } while (0)
118: #define UMUL_TIME 46
119: #ifndef LONGLONG_STANDALONE
120: #define udiv_qrnnd(q, r, n1, n0, d) \
121: do { UDItype __r; \
122: (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
123: (r) = __r; \
124: } while (0)
125: extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
126: #define UDIV_TIME 220
127: #endif /* LONGLONG_STANDALONE */
128: #ifdef __alpha_cix__
129: #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
130: #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
131: #define COUNT_LEADING_ZEROS_0 64
132: #else
133: #define count_leading_zeros(COUNT,X) \
134: do { \
135: UDItype __xr = (X), __t, __a; \
136: __t = __builtin_alpha_cmpbge (0, __xr); \
137: __a = __clz_tab[__t ^ 0xff] - 1; \
138: __t = __builtin_alpha_extbl (__xr, __a); \
139: (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
140: } while (0)
141: #define count_trailing_zeros(COUNT,X) \
142: do { \
143: UDItype __xr = (X), __t, __a; \
144: __t = __builtin_alpha_cmpbge (0, __xr); \
145: __t = ~__t & -~__t; \
146: __a = ((__t & 0xCC) != 0) * 2; \
147: __a += ((__t & 0xF0) != 0) * 4; \
148: __a += ((__t & 0xAA) != 0); \
149: __t = __builtin_alpha_extbl (__xr, __a); \
150: __a <<= 3; \
151: __t &= -__t; \
152: __a += ((__t & 0xCC) != 0) * 2; \
153: __a += ((__t & 0xF0) != 0) * 4; \
154: __a += ((__t & 0xAA) != 0); \
155: (COUNT) = __a; \
156: } while (0)
157: #endif /* __alpha_cix__ */
158: #endif /* __alpha */
159:
160: #if defined (__arc__) && W_TYPE_SIZE == 32
161: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
162: __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
163: : "=r" ((USItype) (sh)), \
164: "=&r" ((USItype) (sl)) \
165: : "%r" ((USItype) (ah)), \
166: "rIJ" ((USItype) (bh)), \
167: "%r" ((USItype) (al)), \
168: "rIJ" ((USItype) (bl)))
169: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
170: __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
171: : "=r" ((USItype) (sh)), \
172: "=&r" ((USItype) (sl)) \
173: : "r" ((USItype) (ah)), \
174: "rIJ" ((USItype) (bh)), \
175: "r" ((USItype) (al)), \
176: "rIJ" ((USItype) (bl)))
177: /* Call libgcc routine. */
178: #define umul_ppmm(w1, w0, u, v) \
179: do { \
180: DWunion __w; \
181: __w.ll = __umulsidi3 (u, v); \
182: w1 = __w.s.high; \
183: w0 = __w.s.low; \
184: } while (0)
185: #define __umulsidi3 __umulsidi3
186: UDItype __umulsidi3 (USItype, USItype);
187: #endif
188:
189: #if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
190: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
191: __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
192: : "=r" ((USItype) (sh)), \
193: "=&r" ((USItype) (sl)) \
194: : "%r" ((USItype) (ah)), \
195: "rI" ((USItype) (bh)), \
196: "%r" ((USItype) (al)), \
197: "rI" ((USItype) (bl)) __CLOBBER_CC)
198: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
199: __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
200: : "=r" ((USItype) (sh)), \
201: "=&r" ((USItype) (sl)) \
202: : "r" ((USItype) (ah)), \
203: "rI" ((USItype) (bh)), \
204: "r" ((USItype) (al)), \
205: "rI" ((USItype) (bl)) __CLOBBER_CC)
206: #define umul_ppmm(xh, xl, a, b) \
207: {register USItype __t0, __t1, __t2; \
208: __asm__ ("%@ Inlined umul_ppmm\n" \
209: " mov %2, %5, lsr #16\n" \
210: " mov %0, %6, lsr #16\n" \
211: " bic %3, %5, %2, lsl #16\n" \
212: " bic %4, %6, %0, lsl #16\n" \
213: " mul %1, %3, %4\n" \
214: " mul %4, %2, %4\n" \
215: " mul %3, %0, %3\n" \
216: " mul %0, %2, %0\n" \
217: " adds %3, %4, %3\n" \
218: " addcs %0, %0, #65536\n" \
219: " adds %1, %1, %3, lsl #16\n" \
220: " adc %0, %0, %3, lsr #16" \
221: : "=&r" ((USItype) (xh)), \
222: "=r" ((USItype) (xl)), \
223: "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
224: : "r" ((USItype) (a)), \
225: "r" ((USItype) (b)) __CLOBBER_CC );}
226: #define UMUL_TIME 20
227: #define UDIV_TIME 100
228: #endif /* __arm__ */
229:
230: #if defined (__hppa) && W_TYPE_SIZE == 32
231: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
232: __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
233: : "=r" ((USItype) (sh)), \
234: "=&r" ((USItype) (sl)) \
235: : "%rM" ((USItype) (ah)), \
236: "rM" ((USItype) (bh)), \
237: "%rM" ((USItype) (al)), \
238: "rM" ((USItype) (bl)))
239: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
240: __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
241: : "=r" ((USItype) (sh)), \
242: "=&r" ((USItype) (sl)) \
243: : "rM" ((USItype) (ah)), \
244: "rM" ((USItype) (bh)), \
245: "rM" ((USItype) (al)), \
246: "rM" ((USItype) (bl)))
247: #if defined (_PA_RISC1_1)
248: #define umul_ppmm(w1, w0, u, v) \
249: do { \
250: union \
251: { \
252: UDItype __f; \
253: struct {USItype __w1, __w0;} __w1w0; \
254: } __t; \
255: __asm__ ("xmpyu %1,%2,%0" \
256: : "=x" (__t.__f) \
257: : "x" ((USItype) (u)), \
258: "x" ((USItype) (v))); \
259: (w1) = __t.__w1w0.__w1; \
260: (w0) = __t.__w1w0.__w0; \
261: } while (0)
262: #define UMUL_TIME 8
263: #else
264: #define UMUL_TIME 30
265: #endif
266: #define UDIV_TIME 40
267: #define count_leading_zeros(count, x) \
268: do { \
269: USItype __tmp; \
270: __asm__ ( \
271: "ldi 1,%0\n" \
272: " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
273: " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
274: " ldo 16(%0),%0 ; Yes. Perform add.\n" \
275: " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
276: " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
277: " ldo 8(%0),%0 ; Yes. Perform add.\n" \
278: " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
279: " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
280: " ldo 4(%0),%0 ; Yes. Perform add.\n" \
281: " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
282: " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
283: " ldo 2(%0),%0 ; Yes. Perform add.\n" \
284: " extru %1,30,1,%1 ; Extract bit 1.\n" \
285: " sub %0,%1,%0 ; Subtract it.\n" \
286: : "=r" (count), "=r" (__tmp) : "1" (x)); \
287: } while (0)
288: #endif
289:
290: #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
291: #define smul_ppmm(xh, xl, m0, m1) \
292: do { \
293: union {DItype __ll; \
294: struct {USItype __h, __l;} __i; \
295: } __x; \
296: __asm__ ("lr %N0,%1\n\tmr %0,%2" \
297: : "=&r" (__x.__ll) \
298: : "r" (m0), "r" (m1)); \
299: (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
300: } while (0)
301: #define sdiv_qrnnd(q, r, n1, n0, d) \
302: do { \
303: union {DItype __ll; \
304: struct {USItype __h, __l;} __i; \
305: } __x; \
306: __x.__i.__h = n1; __x.__i.__l = n0; \
307: __asm__ ("dr %0,%2" \
308: : "=r" (__x.__ll) \
309: : "0" (__x.__ll), "r" (d)); \
310: (q) = __x.__i.__l; (r) = __x.__i.__h; \
311: } while (0)
312: #endif
313:
314: #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
315: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
316: __asm__ ("addl %5,%1\n\tadcl %3,%0" \
317: : "=r" ((USItype) (sh)), \
318: "=&r" ((USItype) (sl)) \
319: : "%0" ((USItype) (ah)), \
320: "g" ((USItype) (bh)), \
321: "%1" ((USItype) (al)), \
322: "g" ((USItype) (bl)))
323: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
324: __asm__ ("subl %5,%1\n\tsbbl %3,%0" \
325: : "=r" ((USItype) (sh)), \
326: "=&r" ((USItype) (sl)) \
327: : "0" ((USItype) (ah)), \
328: "g" ((USItype) (bh)), \
329: "1" ((USItype) (al)), \
330: "g" ((USItype) (bl)))
331: #define umul_ppmm(w1, w0, u, v) \
332: __asm__ ("mull %3" \
333: : "=a" ((USItype) (w0)), \
334: "=d" ((USItype) (w1)) \
335: : "%0" ((USItype) (u)), \
336: "rm" ((USItype) (v)))
337: #define udiv_qrnnd(q, r, n1, n0, dv) \
338: __asm__ ("divl %4" \
339: : "=a" ((USItype) (q)), \
340: "=d" ((USItype) (r)) \
341: : "0" ((USItype) (n0)), \
342: "1" ((USItype) (n1)), \
343: "rm" ((USItype) (dv)))
344: #define count_leading_zeros(count, x) \
345: do { \
346: USItype __cbtmp; \
347: __asm__ ("bsrl %1,%0" \
348: : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
349: (count) = __cbtmp ^ 31; \
350: } while (0)
351: #define count_trailing_zeros(count, x) \
352: __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
353: #define UMUL_TIME 40
354: #define UDIV_TIME 40
355: #endif /* 80x86 */
356:
357: #if defined (__i960__) && W_TYPE_SIZE == 32
358: #define umul_ppmm(w1, w0, u, v) \
359: ({union {UDItype __ll; \
360: struct {USItype __l, __h;} __i; \
361: } __xx; \
362: __asm__ ("emul %2,%1,%0" \
363: : "=d" (__xx.__ll) \
364: : "%dI" ((USItype) (u)), \
365: "dI" ((USItype) (v))); \
366: (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
367: #define __umulsidi3(u, v) \
368: ({UDItype __w; \
369: __asm__ ("emul %2,%1,%0" \
370: : "=d" (__w) \
371: : "%dI" ((USItype) (u)), \
372: "dI" ((USItype) (v))); \
373: __w; })
374: #endif /* __i960__ */
375:
376: #if defined (__M32R__) && W_TYPE_SIZE == 32
377: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
378: /* The cmp clears the condition bit. */ \
379: __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
380: : "=r" ((USItype) (sh)), \
381: "=&r" ((USItype) (sl)) \
382: : "0" ((USItype) (ah)), \
383: "r" ((USItype) (bh)), \
384: "1" ((USItype) (al)), \
385: "r" ((USItype) (bl)) \
386: : "cbit")
387: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
388: /* The cmp clears the condition bit. */ \
389: __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
390: : "=r" ((USItype) (sh)), \
391: "=&r" ((USItype) (sl)) \
392: : "0" ((USItype) (ah)), \
393: "r" ((USItype) (bh)), \
394: "1" ((USItype) (al)), \
395: "r" ((USItype) (bl)) \
396: : "cbit")
397: #endif /* __M32R__ */
398:
399: #if defined (__mc68000__) && W_TYPE_SIZE == 32
400: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
401: __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
402: : "=d" ((USItype) (sh)), \
403: "=&d" ((USItype) (sl)) \
404: : "%0" ((USItype) (ah)), \
405: "d" ((USItype) (bh)), \
406: "%1" ((USItype) (al)), \
407: "g" ((USItype) (bl)))
408: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
409: __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
410: : "=d" ((USItype) (sh)), \
411: "=&d" ((USItype) (sl)) \
412: : "0" ((USItype) (ah)), \
413: "d" ((USItype) (bh)), \
414: "1" ((USItype) (al)), \
415: "g" ((USItype) (bl)))
416:
417: /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
418: #if (defined (__mc68020__) && !defined (__mc68060__))
419: #define umul_ppmm(w1, w0, u, v) \
420: __asm__ ("mulu%.l %3,%1:%0" \
421: : "=d" ((USItype) (w0)), \
422: "=d" ((USItype) (w1)) \
423: : "%0" ((USItype) (u)), \
424: "dmi" ((USItype) (v)))
425: #define UMUL_TIME 45
426: #define udiv_qrnnd(q, r, n1, n0, d) \
427: __asm__ ("divu%.l %4,%1:%0" \
428: : "=d" ((USItype) (q)), \
429: "=d" ((USItype) (r)) \
430: : "0" ((USItype) (n0)), \
431: "1" ((USItype) (n1)), \
432: "dmi" ((USItype) (d)))
433: #define UDIV_TIME 90
434: #define sdiv_qrnnd(q, r, n1, n0, d) \
435: __asm__ ("divs%.l %4,%1:%0" \
436: : "=d" ((USItype) (q)), \
437: "=d" ((USItype) (r)) \
438: : "0" ((USItype) (n0)), \
439: "1" ((USItype) (n1)), \
440: "dmi" ((USItype) (d)))
441:
442: #elif defined (__mcoldfire__) /* not mc68020 */
443:
444: #define umul_ppmm(xh, xl, a, b) \
445: __asm__ ("| Inlined umul_ppmm\n" \
446: " move%.l %2,%/d0\n" \
447: " move%.l %3,%/d1\n" \
448: " move%.l %/d0,%/d2\n" \
449: " swap %/d0\n" \
450: " move%.l %/d1,%/d3\n" \
451: " swap %/d1\n" \
452: " move%.w %/d2,%/d4\n" \
453: " mulu %/d3,%/d4\n" \
454: " mulu %/d1,%/d2\n" \
455: " mulu %/d0,%/d3\n" \
456: " mulu %/d0,%/d1\n" \
457: " move%.l %/d4,%/d0\n" \
458: " clr%.w %/d0\n" \
459: " swap %/d0\n" \
460: " add%.l %/d0,%/d2\n" \
461: " add%.l %/d3,%/d2\n" \
462: " jcc 1f\n" \
463: " add%.l %#65536,%/d1\n" \
464: "1: swap %/d2\n" \
465: " moveq %#0,%/d0\n" \
466: " move%.w %/d2,%/d0\n" \
467: " move%.w %/d4,%/d2\n" \
468: " move%.l %/d2,%1\n" \
469: " add%.l %/d1,%/d0\n" \
470: " move%.l %/d0,%0" \
471: : "=g" ((USItype) (xh)), \
472: "=g" ((USItype) (xl)) \
473: : "g" ((USItype) (a)), \
474: "g" ((USItype) (b)) \
475: : "d0", "d1", "d2", "d3", "d4")
476: #define UMUL_TIME 100
477: #define UDIV_TIME 400
478: #else /* not ColdFire */
479: /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
480: #define umul_ppmm(xh, xl, a, b) \
481: __asm__ ("| Inlined umul_ppmm\n" \
482: " move%.l %2,%/d0\n" \
483: " move%.l %3,%/d1\n" \
484: " move%.l %/d0,%/d2\n" \
485: " swap %/d0\n" \
486: " move%.l %/d1,%/d3\n" \
487: " swap %/d1\n" \
488: " move%.w %/d2,%/d4\n" \
489: " mulu %/d3,%/d4\n" \
490: " mulu %/d1,%/d2\n" \
491: " mulu %/d0,%/d3\n" \
492: " mulu %/d0,%/d1\n" \
493: " move%.l %/d4,%/d0\n" \
494: " eor%.w %/d0,%/d0\n" \
495: " swap %/d0\n" \
496: " add%.l %/d0,%/d2\n" \
497: " add%.l %/d3,%/d2\n" \
498: " jcc 1f\n" \
499: " add%.l %#65536,%/d1\n" \
500: "1: swap %/d2\n" \
501: " moveq %#0,%/d0\n" \
502: " move%.w %/d2,%/d0\n" \
503: " move%.w %/d4,%/d2\n" \
504: " move%.l %/d2,%1\n" \
505: " add%.l %/d1,%/d0\n" \
506: " move%.l %/d0,%0" \
507: : "=g" ((USItype) (xh)), \
508: "=g" ((USItype) (xl)) \
509: : "g" ((USItype) (a)), \
510: "g" ((USItype) (b)) \
511: : "d0", "d1", "d2", "d3", "d4")
512: #define UMUL_TIME 100
513: #define UDIV_TIME 400
514:
515: #endif /* not mc68020 */
516:
517: /* The '020, '030, '040 and '060 have bitfield insns.
518: cpu32 disguises as a 68020, but lacks them. */
519: #if defined (__mc68020__) && !defined (__mcpu32__)
520: #define count_leading_zeros(count, x) \
521: __asm__ ("bfffo %1{%b2:%b2},%0" \
522: : "=d" ((USItype) (count)) \
523: : "od" ((USItype) (x)), "n" (0))
524: #endif
525: #endif /* mc68000 */
526:
527: #if defined (__m88000__) && W_TYPE_SIZE == 32
528: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
529: __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
530: : "=r" ((USItype) (sh)), \
531: "=&r" ((USItype) (sl)) \
532: : "%rJ" ((USItype) (ah)), \
533: "rJ" ((USItype) (bh)), \
534: "%rJ" ((USItype) (al)), \
535: "rJ" ((USItype) (bl)))
536: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
537: __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
538: : "=r" ((USItype) (sh)), \
539: "=&r" ((USItype) (sl)) \
540: : "rJ" ((USItype) (ah)), \
541: "rJ" ((USItype) (bh)), \
542: "rJ" ((USItype) (al)), \
543: "rJ" ((USItype) (bl)))
544: #define count_leading_zeros(count, x) \
545: do { \
546: USItype __cbtmp; \
547: __asm__ ("ff1 %0,%1" \
548: : "=r" (__cbtmp) \
549: : "r" ((USItype) (x))); \
550: (count) = __cbtmp ^ 31; \
551: } while (0)
552: #define COUNT_LEADING_ZEROS_0 63 /* sic */
553: #if defined (__mc88110__)
554: #define umul_ppmm(wh, wl, u, v) \
555: do { \
556: union {UDItype __ll; \
557: struct {USItype __h, __l;} __i; \
558: } __xx; \
559: __asm__ ("mulu.d %0,%1,%2" \
560: : "=r" (__xx.__ll) \
561: : "r" ((USItype) (u)), \
562: "r" ((USItype) (v))); \
563: (wh) = __xx.__i.__h; \
564: (wl) = __xx.__i.__l; \
565: } while (0)
566: #define udiv_qrnnd(q, r, n1, n0, d) \
567: ({union {UDItype __ll; \
568: struct {USItype __h, __l;} __i; \
569: } __xx; \
570: USItype __q; \
571: __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
572: __asm__ ("divu.d %0,%1,%2" \
573: : "=r" (__q) \
574: : "r" (__xx.__ll), \
575: "r" ((USItype) (d))); \
576: (r) = (n0) - __q * (d); (q) = __q; })
577: #define UMUL_TIME 5
578: #define UDIV_TIME 25
579: #else
580: #define UMUL_TIME 17
581: #define UDIV_TIME 150
582: #endif /* __mc88110__ */
583: #endif /* __m88000__ */
584:
585: #if defined (__mips__) && W_TYPE_SIZE == 32
586: #define umul_ppmm(w1, w0, u, v) \
587: __asm__ ("multu %2,%3" \
588: : "=l" ((USItype) (w0)), \
589: "=h" ((USItype) (w1)) \
590: : "d" ((USItype) (u)), \
591: "d" ((USItype) (v)))
592: #define UMUL_TIME 10
593: #define UDIV_TIME 100
594: #endif /* __mips__ */
595:
596: #if defined (__ns32000__) && W_TYPE_SIZE == 32
597: #define umul_ppmm(w1, w0, u, v) \
598: ({union {UDItype __ll; \
599: struct {USItype __l, __h;} __i; \
600: } __xx; \
601: __asm__ ("meid %2,%0" \
602: : "=g" (__xx.__ll) \
603: : "%0" ((USItype) (u)), \
604: "g" ((USItype) (v))); \
605: (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
606: #define __umulsidi3(u, v) \
607: ({UDItype __w; \
608: __asm__ ("meid %2,%0" \
609: : "=g" (__w) \
610: : "%0" ((USItype) (u)), \
611: "g" ((USItype) (v))); \
612: __w; })
613: #define udiv_qrnnd(q, r, n1, n0, d) \
614: ({union {UDItype __ll; \
615: struct {USItype __l, __h;} __i; \
616: } __xx; \
617: __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
618: __asm__ ("deid %2,%0" \
619: : "=g" (__xx.__ll) \
620: : "0" (__xx.__ll), \
621: "g" ((USItype) (d))); \
622: (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
623: #define count_trailing_zeros(count,x) \
624: do { \
625: __asm__ ("ffsd %2,%0" \
626: : "=r" ((USItype) (count)) \
627: : "0" ((USItype) 0), \
628: "r" ((USItype) (x))); \
629: } while (0)
630: #endif /* __ns32000__ */
631:
632: /* FIXME: We should test _IBMR2 here when we add assembly support for the
633: system vendor compilers.
634: FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
635: enough, since that hits ARM and m68k too. */
636: #if (defined (_ARCH_PPC) /* AIX */ \
637: || defined (_ARCH_PWR) /* AIX */ \
638: || defined (_ARCH_COM) /* AIX */ \
639: || defined (__powerpc__) /* gcc */ \
640: || defined (__POWERPC__) /* BEOS */ \
641: || defined (__ppc__) /* Darwin */ \
642: || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
643: || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
644: && CPU_FAMILY == PPC) \
645: ) && W_TYPE_SIZE == 32
646: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
647: do { \
648: if (__builtin_constant_p (bh) && (bh) == 0) \
649: __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
650: : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
651: else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
652: __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
653: : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
654: else \
655: __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
656: : "=r" (sh), "=&r" (sl) \
657: : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
658: } while (0)
659: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
660: do { \
661: if (__builtin_constant_p (ah) && (ah) == 0) \
662: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
663: : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
664: else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
665: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
666: : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
667: else if (__builtin_constant_p (bh) && (bh) == 0) \
668: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
669: : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
670: else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
671: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
672: : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
673: else \
674: __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
675: : "=r" (sh), "=&r" (sl) \
676: : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
677: } while (0)
678: #define count_leading_zeros(count, x) \
679: __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
680: #define COUNT_LEADING_ZEROS_0 32
681: #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
682: || defined (__ppc__) \
683: || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
684: || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
685: && CPU_FAMILY == PPC)
686: #define umul_ppmm(ph, pl, m0, m1) \
687: do { \
688: USItype __m0 = (m0), __m1 = (m1); \
689: __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
690: (pl) = __m0 * __m1; \
691: } while (0)
692: #define UMUL_TIME 15
693: #define smul_ppmm(ph, pl, m0, m1) \
694: do { \
695: SItype __m0 = (m0), __m1 = (m1); \
696: __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
697: (pl) = __m0 * __m1; \
698: } while (0)
699: #define SMUL_TIME 14
700: #define UDIV_TIME 120
701: #elif defined (_ARCH_PWR)
702: #define UMUL_TIME 8
703: #define smul_ppmm(xh, xl, m0, m1) \
704: __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
705: #define SMUL_TIME 4
706: #define sdiv_qrnnd(q, r, nh, nl, d) \
707: __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
708: #define UDIV_TIME 100
709: #endif
710: #endif /* 32-bit POWER architecture variants. */
711:
712: /* We should test _IBMR2 here when we add assembly support for the system
713: vendor compilers. */
714: #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
715: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
716: do { \
717: if (__builtin_constant_p (bh) && (bh) == 0) \
718: __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
719: : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
720: else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
721: __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
722: : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
723: else \
724: __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
725: : "=r" (sh), "=&r" (sl) \
726: : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
727: } while (0)
728: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
729: do { \
730: if (__builtin_constant_p (ah) && (ah) == 0) \
731: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
732: : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
733: else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
734: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
735: : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
736: else if (__builtin_constant_p (bh) && (bh) == 0) \
737: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
738: : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
739: else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
740: __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
741: : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
742: else \
743: __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
744: : "=r" (sh), "=&r" (sl) \
745: : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
746: } while (0)
747: #define count_leading_zeros(count, x) \
748: __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
749: #define COUNT_LEADING_ZEROS_0 64
750: #define umul_ppmm(ph, pl, m0, m1) \
751: do { \
752: UDItype __m0 = (m0), __m1 = (m1); \
753: __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
754: (pl) = __m0 * __m1; \
755: } while (0)
756: #define UMUL_TIME 15
757: #define smul_ppmm(ph, pl, m0, m1) \
758: do { \
759: DItype __m0 = (m0), __m1 = (m1); \
760: __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
761: (pl) = __m0 * __m1; \
762: } while (0)
763: #define SMUL_TIME 14 /* ??? */
764: #define UDIV_TIME 120 /* ??? */
765: #endif /* 64-bit PowerPC. */
766:
767: #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
768: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
769: __asm__ ("a %1,%5\n\tae %0,%3" \
770: : "=r" ((USItype) (sh)), \
771: "=&r" ((USItype) (sl)) \
772: : "%0" ((USItype) (ah)), \
773: "r" ((USItype) (bh)), \
774: "%1" ((USItype) (al)), \
775: "r" ((USItype) (bl)))
776: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
777: __asm__ ("s %1,%5\n\tse %0,%3" \
778: : "=r" ((USItype) (sh)), \
779: "=&r" ((USItype) (sl)) \
780: : "0" ((USItype) (ah)), \
781: "r" ((USItype) (bh)), \
782: "1" ((USItype) (al)), \
783: "r" ((USItype) (bl)))
784: #define umul_ppmm(ph, pl, m0, m1) \
785: do { \
786: USItype __m0 = (m0), __m1 = (m1); \
787: __asm__ ( \
788: "s r2,r2\n" \
789: " mts r10,%2\n" \
790: " m r2,%3\n" \
791: " m r2,%3\n" \
792: " m r2,%3\n" \
793: " m r2,%3\n" \
794: " m r2,%3\n" \
795: " m r2,%3\n" \
796: " m r2,%3\n" \
797: " m r2,%3\n" \
798: " m r2,%3\n" \
799: " m r2,%3\n" \
800: " m r2,%3\n" \
801: " m r2,%3\n" \
802: " m r2,%3\n" \
803: " m r2,%3\n" \
804: " m r2,%3\n" \
805: " m r2,%3\n" \
806: " cas %0,r2,r0\n" \
807: " mfs r10,%1" \
808: : "=r" ((USItype) (ph)), \
809: "=r" ((USItype) (pl)) \
810: : "%r" (__m0), \
811: "r" (__m1) \
812: : "r2"); \
813: (ph) += ((((SItype) __m0 >> 31) & __m1) \
814: + (((SItype) __m1 >> 31) & __m0)); \
815: } while (0)
816: #define UMUL_TIME 20
817: #define UDIV_TIME 200
818: #define count_leading_zeros(count, x) \
819: do { \
820: if ((x) >= 0x10000) \
821: __asm__ ("clz %0,%1" \
822: : "=r" ((USItype) (count)) \
823: : "r" ((USItype) (x) >> 16)); \
824: else \
825: { \
826: __asm__ ("clz %0,%1" \
827: : "=r" ((USItype) (count)) \
828: : "r" ((USItype) (x))); \
829: (count) += 16; \
830: } \
831: } while (0)
832: #endif
833:
834: #if defined (__sh2__) && W_TYPE_SIZE == 32
835: #define umul_ppmm(w1, w0, u, v) \
836: __asm__ ( \
837: "dmulu.l %2,%3\n\tsts macl,%1\n\tsts mach,%0" \
838: : "=r" ((USItype)(w1)), \
839: "=r" ((USItype)(w0)) \
840: : "r" ((USItype)(u)), \
841: "r" ((USItype)(v)) \
842: : "macl", "mach")
843: #define UMUL_TIME 5
844: #endif
845:
846: #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
847: #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
848: #define count_leading_zeros(count, x) \
849: do \
850: { \
851: UDItype x_ = (USItype)(x); \
852: SItype c_; \
853: \
854: __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
855: (count) = c_ - 31; \
856: } \
857: while (0)
858: #define COUNT_LEADING_ZEROS_0 32
859: #endif
860:
861: #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
862: && W_TYPE_SIZE == 32
863: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
864: __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
865: : "=r" ((USItype) (sh)), \
866: "=&r" ((USItype) (sl)) \
867: : "%rJ" ((USItype) (ah)), \
868: "rI" ((USItype) (bh)), \
869: "%rJ" ((USItype) (al)), \
870: "rI" ((USItype) (bl)) \
871: __CLOBBER_CC)
872: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
873: __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
874: : "=r" ((USItype) (sh)), \
875: "=&r" ((USItype) (sl)) \
876: : "rJ" ((USItype) (ah)), \
877: "rI" ((USItype) (bh)), \
878: "rJ" ((USItype) (al)), \
879: "rI" ((USItype) (bl)) \
880: __CLOBBER_CC)
881: #if defined (__sparc_v8__)
882: #define umul_ppmm(w1, w0, u, v) \
883: __asm__ ("umul %2,%3,%1;rd %%y,%0" \
884: : "=r" ((USItype) (w1)), \
885: "=r" ((USItype) (w0)) \
886: : "r" ((USItype) (u)), \
887: "r" ((USItype) (v)))
888: #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
889: __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
890: : "=&r" ((USItype) (__q)), \
891: "=&r" ((USItype) (__r)) \
892: : "r" ((USItype) (__n1)), \
893: "r" ((USItype) (__n0)), \
894: "r" ((USItype) (__d)))
895: #else
896: #if defined (__sparclite__)
897: /* This has hardware multiply but not divide. It also has two additional
898: instructions scan (ffs from high bit) and divscc. */
899: #define umul_ppmm(w1, w0, u, v) \
900: __asm__ ("umul %2,%3,%1;rd %%y,%0" \
901: : "=r" ((USItype) (w1)), \
902: "=r" ((USItype) (w0)) \
903: : "r" ((USItype) (u)), \
904: "r" ((USItype) (v)))
905: #define udiv_qrnnd(q, r, n1, n0, d) \
906: __asm__ ("! Inlined udiv_qrnnd\n" \
907: " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
908: " tst %%g0\n" \
909: " divscc %3,%4,%%g1\n" \
910: " divscc %%g1,%4,%%g1\n" \
911: " divscc %%g1,%4,%%g1\n" \
912: " divscc %%g1,%4,%%g1\n" \
913: " divscc %%g1,%4,%%g1\n" \
914: " divscc %%g1,%4,%%g1\n" \
915: " divscc %%g1,%4,%%g1\n" \
916: " divscc %%g1,%4,%%g1\n" \
917: " divscc %%g1,%4,%%g1\n" \
918: " divscc %%g1,%4,%%g1\n" \
919: " divscc %%g1,%4,%%g1\n" \
920: " divscc %%g1,%4,%%g1\n" \
921: " divscc %%g1,%4,%%g1\n" \
922: " divscc %%g1,%4,%%g1\n" \
923: " divscc %%g1,%4,%%g1\n" \
924: " divscc %%g1,%4,%%g1\n" \
925: " divscc %%g1,%4,%%g1\n" \
926: " divscc %%g1,%4,%%g1\n" \
927: " divscc %%g1,%4,%%g1\n" \
928: " divscc %%g1,%4,%%g1\n" \
929: " divscc %%g1,%4,%%g1\n" \
930: " divscc %%g1,%4,%%g1\n" \
931: " divscc %%g1,%4,%%g1\n" \
932: " divscc %%g1,%4,%%g1\n" \
933: " divscc %%g1,%4,%%g1\n" \
934: " divscc %%g1,%4,%%g1\n" \
935: " divscc %%g1,%4,%%g1\n" \
936: " divscc %%g1,%4,%%g1\n" \
937: " divscc %%g1,%4,%%g1\n" \
938: " divscc %%g1,%4,%%g1\n" \
939: " divscc %%g1,%4,%%g1\n" \
940: " divscc %%g1,%4,%0\n" \
941: " rd %%y,%1\n" \
942: " bl,a 1f\n" \
943: " add %1,%4,%1\n" \
944: "1: ! End of inline udiv_qrnnd" \
945: : "=r" ((USItype) (q)), \
946: "=r" ((USItype) (r)) \
947: : "r" ((USItype) (n1)), \
948: "r" ((USItype) (n0)), \
949: "rI" ((USItype) (d)) \
950: : "g1" __AND_CLOBBER_CC)
951: #define UDIV_TIME 37
952: #define count_leading_zeros(count, x) \
953: do { \
954: __asm__ ("scan %1,1,%0" \
955: : "=r" ((USItype) (count)) \
956: : "r" ((USItype) (x))); \
957: } while (0)
958: /* Early sparclites return 63 for an argument of 0, but they warn that future
959: implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
960: undefined. */
961: #else
962: /* SPARC without integer multiplication and divide instructions.
963: (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
964: #define umul_ppmm(w1, w0, u, v) \
965: __asm__ ("! Inlined umul_ppmm\n" \
966: " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
967: " sra %3,31,%%o5 ! Don't move this insn\n" \
968: " and %2,%%o5,%%o5 ! Don't move this insn\n" \
969: " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
970: " mulscc %%g1,%3,%%g1\n" \
971: " mulscc %%g1,%3,%%g1\n" \
972: " mulscc %%g1,%3,%%g1\n" \
973: " mulscc %%g1,%3,%%g1\n" \
974: " mulscc %%g1,%3,%%g1\n" \
975: " mulscc %%g1,%3,%%g1\n" \
976: " mulscc %%g1,%3,%%g1\n" \
977: " mulscc %%g1,%3,%%g1\n" \
978: " mulscc %%g1,%3,%%g1\n" \
979: " mulscc %%g1,%3,%%g1\n" \
980: " mulscc %%g1,%3,%%g1\n" \
981: " mulscc %%g1,%3,%%g1\n" \
982: " mulscc %%g1,%3,%%g1\n" \
983: " mulscc %%g1,%3,%%g1\n" \
984: " mulscc %%g1,%3,%%g1\n" \
985: " mulscc %%g1,%3,%%g1\n" \
986: " mulscc %%g1,%3,%%g1\n" \
987: " mulscc %%g1,%3,%%g1\n" \
988: " mulscc %%g1,%3,%%g1\n" \
989: " mulscc %%g1,%3,%%g1\n" \
990: " mulscc %%g1,%3,%%g1\n" \
991: " mulscc %%g1,%3,%%g1\n" \
992: " mulscc %%g1,%3,%%g1\n" \
993: " mulscc %%g1,%3,%%g1\n" \
994: " mulscc %%g1,%3,%%g1\n" \
995: " mulscc %%g1,%3,%%g1\n" \
996: " mulscc %%g1,%3,%%g1\n" \
997: " mulscc %%g1,%3,%%g1\n" \
998: " mulscc %%g1,%3,%%g1\n" \
999: " mulscc %%g1,%3,%%g1\n" \
1000: " mulscc %%g1,%3,%%g1\n" \
1001: " mulscc %%g1,%3,%%g1\n" \
1002: " mulscc %%g1,0,%%g1\n" \
1003: " add %%g1,%%o5,%0\n" \
1004: " rd %%y,%1" \
1005: : "=r" ((USItype) (w1)), \
1006: "=r" ((USItype) (w0)) \
1007: : "%rI" ((USItype) (u)), \
1008: "r" ((USItype) (v)) \
1009: : "g1", "o5" __AND_CLOBBER_CC)
1010: #define UMUL_TIME 39 /* 39 instructions */
1011: /* It's quite necessary to add this much assembler for the sparc.
1012: The default udiv_qrnnd (in C) is more than 10 times slower! */
1013: #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1014: __asm__ ("! Inlined udiv_qrnnd\n" \
1015: " mov 32,%%g1\n" \
1016: " subcc %1,%2,%%g0\n" \
1017: "1: bcs 5f\n" \
1018: " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1019: " sub %1,%2,%1 ! this kills msb of n\n" \
1020: " addx %1,%1,%1 ! so this can't give carry\n" \
1021: " subcc %%g1,1,%%g1\n" \
1022: "2: bne 1b\n" \
1023: " subcc %1,%2,%%g0\n" \
1024: " bcs 3f\n" \
1025: " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1026: " b 3f\n" \
1027: " sub %1,%2,%1 ! this kills msb of n\n" \
1028: "4: sub %1,%2,%1\n" \
1029: "5: addxcc %1,%1,%1\n" \
1030: " bcc 2b\n" \
1031: " subcc %%g1,1,%%g1\n" \
1032: "! Got carry from n. Subtract next step to cancel this carry.\n" \
1033: " bne 4b\n" \
1034: " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1035: " sub %1,%2,%1\n" \
1036: "3: xnor %0,0,%0\n" \
1037: " ! End of inline udiv_qrnnd" \
1038: : "=&r" ((USItype) (__q)), \
1039: "=&r" ((USItype) (__r)) \
1040: : "r" ((USItype) (__d)), \
1041: "1" ((USItype) (__n1)), \
1042: "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1043: #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1044: #endif /* __sparclite__ */
1045: #endif /* __sparc_v8__ */
1046: #endif /* sparc32 */
1047:
1048: #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1049: && W_TYPE_SIZE == 64
1050: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1051: __asm__ ("addcc %r4,%5,%1\n\t" \
1052: "add %r2,%3,%0\n\t" \
1053: "bcs,a,pn %%xcc, 1f\n\t" \
1054: "add %0, 1, %0\n" \
1055: "1:" \
1056: : "=r" ((UDItype)(sh)), \
1057: "=&r" ((UDItype)(sl)) \
1058: : "%rJ" ((UDItype)(ah)), \
1059: "rI" ((UDItype)(bh)), \
1060: "%rJ" ((UDItype)(al)), \
1061: "rI" ((UDItype)(bl)) \
1062: __CLOBBER_CC)
1063:
1064: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1065: __asm__ ("subcc %r4,%5,%1\n\t" \
1066: "sub %r2,%3,%0\n\t" \
1067: "bcs,a,pn %%xcc, 1f\n\t" \
1068: "sub %0, 1, %0\n\t" \
1069: "1:" \
1070: : "=r" ((UDItype)(sh)), \
1071: "=&r" ((UDItype)(sl)) \
1072: : "rJ" ((UDItype)(ah)), \
1073: "rI" ((UDItype)(bh)), \
1074: "rJ" ((UDItype)(al)), \
1075: "rI" ((UDItype)(bl)) \
1076: __CLOBBER_CC)
1077:
1078: #define umul_ppmm(wh, wl, u, v) \
1079: do { \
1080: UDItype tmp1, tmp2, tmp3, tmp4; \
1081: __asm__ __volatile__ ( \
1082: "srl %7,0,%3\n\t" \
1083: "mulx %3,%6,%1\n\t" \
1084: "srlx %6,32,%2\n\t" \
1085: "mulx %2,%3,%4\n\t" \
1086: "sllx %4,32,%5\n\t" \
1087: "srl %6,0,%3\n\t" \
1088: "sub %1,%5,%5\n\t" \
1089: "srlx %5,32,%5\n\t" \
1090: "addcc %4,%5,%4\n\t" \
1091: "srlx %7,32,%5\n\t" \
1092: "mulx %3,%5,%3\n\t" \
1093: "mulx %2,%5,%5\n\t" \
1094: "sethi %%hi(0x80000000),%2\n\t" \
1095: "addcc %4,%3,%4\n\t" \
1096: "srlx %4,32,%4\n\t" \
1097: "add %2,%2,%2\n\t" \
1098: "movcc %%xcc,%%g0,%2\n\t" \
1099: "addcc %5,%4,%5\n\t" \
1100: "sllx %3,32,%3\n\t" \
1101: "add %1,%3,%1\n\t" \
1102: "add %5,%2,%0" \
1103: : "=r" ((UDItype)(wh)), \
1104: "=&r" ((UDItype)(wl)), \
1105: "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1106: : "r" ((UDItype)(u)), \
1107: "r" ((UDItype)(v)) \
1108: __CLOBBER_CC); \
1109: } while (0)
1110: #define UMUL_TIME 96
1111: #define UDIV_TIME 230
1112: #endif /* sparc64 */
1113:
1114: #if defined (__vax__) && W_TYPE_SIZE == 32
1115: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1116: __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1117: : "=g" ((USItype) (sh)), \
1118: "=&g" ((USItype) (sl)) \
1119: : "%0" ((USItype) (ah)), \
1120: "g" ((USItype) (bh)), \
1121: "%1" ((USItype) (al)), \
1122: "g" ((USItype) (bl)))
1123: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1124: __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1125: : "=g" ((USItype) (sh)), \
1126: "=&g" ((USItype) (sl)) \
1127: : "0" ((USItype) (ah)), \
1128: "g" ((USItype) (bh)), \
1129: "1" ((USItype) (al)), \
1130: "g" ((USItype) (bl)))
1131: #define umul_ppmm(xh, xl, m0, m1) \
1132: do { \
1133: union { \
1134: UDItype __ll; \
1135: struct {USItype __l, __h;} __i; \
1136: } __xx; \
1137: USItype __m0 = (m0), __m1 = (m1); \
1138: __asm__ ("emul %1,%2,$0,%0" \
1139: : "=r" (__xx.__ll) \
1140: : "g" (__m0), \
1141: "g" (__m1)); \
1142: (xh) = __xx.__i.__h; \
1143: (xl) = __xx.__i.__l; \
1144: (xh) += ((((SItype) __m0 >> 31) & __m1) \
1145: + (((SItype) __m1 >> 31) & __m0)); \
1146: } while (0)
1147: #define sdiv_qrnnd(q, r, n1, n0, d) \
1148: do { \
1149: union {DItype __ll; \
1150: struct {SItype __l, __h;} __i; \
1151: } __xx; \
1152: __xx.__i.__h = n1; __xx.__i.__l = n0; \
1153: __asm__ ("ediv %3,%2,%0,%1" \
1154: : "=g" (q), "=g" (r) \
1155: : "g" (__xx.__ll), "g" (d)); \
1156: } while (0)
1157: #endif /* __vax__ */
1158:
1159: #if defined (__z8000__) && W_TYPE_SIZE == 16
1160: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1161: __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1162: : "=r" ((unsigned int)(sh)), \
1163: "=&r" ((unsigned int)(sl)) \
1164: : "%0" ((unsigned int)(ah)), \
1165: "r" ((unsigned int)(bh)), \
1166: "%1" ((unsigned int)(al)), \
1167: "rQR" ((unsigned int)(bl)))
1168: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1169: __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1170: : "=r" ((unsigned int)(sh)), \
1171: "=&r" ((unsigned int)(sl)) \
1172: : "0" ((unsigned int)(ah)), \
1173: "r" ((unsigned int)(bh)), \
1174: "1" ((unsigned int)(al)), \
1175: "rQR" ((unsigned int)(bl)))
1176: #define umul_ppmm(xh, xl, m0, m1) \
1177: do { \
1178: union {long int __ll; \
1179: struct {unsigned int __h, __l;} __i; \
1180: } __xx; \
1181: unsigned int __m0 = (m0), __m1 = (m1); \
1182: __asm__ ("mult %S0,%H3" \
1183: : "=r" (__xx.__i.__h), \
1184: "=r" (__xx.__i.__l) \
1185: : "%1" (__m0), \
1186: "rQR" (__m1)); \
1187: (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1188: (xh) += ((((signed int) __m0 >> 15) & __m1) \
1189: + (((signed int) __m1 >> 15) & __m0)); \
1190: } while (0)
1191: #endif /* __z8000__ */
1192:
1193: #endif /* __GNUC__ */
1194:
1195: /* If this machine has no inline assembler, use C macros. */
1196:
1197: #if !defined (add_ssaaaa)
1198: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1199: do { \
1200: UWtype __x; \
1201: __x = (al) + (bl); \
1202: (sh) = (ah) + (bh) + (__x < (al)); \
1203: (sl) = __x; \
1204: } while (0)
1205: #endif
1206:
1207: #if !defined (sub_ddmmss)
1208: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1209: do { \
1210: UWtype __x; \
1211: __x = (al) - (bl); \
1212: (sh) = (ah) - (bh) - (__x > (al)); \
1213: (sl) = __x; \
1214: } while (0)
1215: #endif
1216:
1217: /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1218: smul_ppmm. */
1219: #if !defined (umul_ppmm) && defined (smul_ppmm)
1220: #define umul_ppmm(w1, w0, u, v) \
1221: do { \
1222: UWtype __w1; \
1223: UWtype __xm0 = (u), __xm1 = (v); \
1224: smul_ppmm (__w1, w0, __xm0, __xm1); \
1225: (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1226: + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1227: } while (0)
1228: #endif
1229:
1230: /* If we still don't have umul_ppmm, define it using plain C. */
1231: #if !defined (umul_ppmm)
1232: #define umul_ppmm(w1, w0, u, v) \
1233: do { \
1234: UWtype __x0, __x1, __x2, __x3; \
1235: UHWtype __ul, __vl, __uh, __vh; \
1236: \
1237: __ul = __ll_lowpart (u); \
1238: __uh = __ll_highpart (u); \
1239: __vl = __ll_lowpart (v); \
1240: __vh = __ll_highpart (v); \
1241: \
1242: __x0 = (UWtype) __ul * __vl; \
1243: __x1 = (UWtype) __ul * __vh; \
1244: __x2 = (UWtype) __uh * __vl; \
1245: __x3 = (UWtype) __uh * __vh; \
1246: \
1247: __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1248: __x1 += __x2; /* but this indeed can */ \
1249: if (__x1 < __x2) /* did we get it? */ \
1250: __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1251: \
1252: (w1) = __x3 + __ll_highpart (__x1); \
1253: (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1254: } while (0)
1255: #endif
1256:
1257: #if !defined (__umulsidi3)
1258: #define __umulsidi3(u, v) \
1259: ({DWunion __w; \
1260: umul_ppmm (__w.s.high, __w.s.low, u, v); \
1261: __w.ll; })
1262: #endif
1263:
1264: /* Define this unconditionally, so it can be used for debugging. */
1265: #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1266: do { \
1267: UWtype __d1, __d0, __q1, __q0; \
1268: UWtype __r1, __r0, __m; \
1269: __d1 = __ll_highpart (d); \
1270: __d0 = __ll_lowpart (d); \
1271: \
1272: __r1 = (n1) % __d1; \
1273: __q1 = (n1) / __d1; \
1274: __m = (UWtype) __q1 * __d0; \
1275: __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1276: if (__r1 < __m) \
1277: { \
1278: __q1--, __r1 += (d); \
1279: if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1280: if (__r1 < __m) \
1281: __q1--, __r1 += (d); \
1282: } \
1283: __r1 -= __m; \
1284: \
1285: __r0 = __r1 % __d1; \
1286: __q0 = __r1 / __d1; \
1287: __m = (UWtype) __q0 * __d0; \
1288: __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1289: if (__r0 < __m) \
1290: { \
1291: __q0--, __r0 += (d); \
1292: if (__r0 >= (d)) \
1293: if (__r0 < __m) \
1294: __q0--, __r0 += (d); \
1295: } \
1296: __r0 -= __m; \
1297: \
1298: (q) = (UWtype) __q1 * __ll_B | __q0; \
1299: (r) = __r0; \
1300: } while (0)
1301:
1302: /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1303: __udiv_w_sdiv (defined in libgcc or elsewhere). */
1304: #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1305: #define udiv_qrnnd(q, r, nh, nl, d) \
1306: do { \
1307: USItype __r; \
1308: (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1309: (r) = __r; \
1310: } while (0)
1311: #endif
1312:
1313: /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1314: #if !defined (udiv_qrnnd)
1315: #define UDIV_NEEDS_NORMALIZATION 1
1316: #define udiv_qrnnd __udiv_qrnnd_c
1317: #endif
1318:
1319: #if !defined (count_leading_zeros)
1320: #define count_leading_zeros(count, x) \
1321: do { \
1322: UWtype __xr = (x); \
1323: UWtype __a; \
1324: \
1325: if (W_TYPE_SIZE <= 32) \
1326: { \
1327: __a = __xr < ((UWtype)1<<2*__BITS4) \
1328: ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1329: : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1330: } \
1331: else \
1332: { \
1333: for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1334: if (((__xr >> __a) & 0xff) != 0) \
1335: break; \
1336: } \
1337: \
1338: (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1339: } while (0)
1340: #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1341: #endif
1342:
1343: #if !defined (count_trailing_zeros)
1344: /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1345: defined in asm, but if it is not, the C version above is good enough. */
1346: #define count_trailing_zeros(count, x) \
1347: do { \
1348: UWtype __ctz_x = (x); \
1349: UWtype __ctz_c; \
1350: count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1351: (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1352: } while (0)
1353: #endif
1354:
1355: #ifndef UDIV_NEEDS_NORMALIZATION
1356: #define UDIV_NEEDS_NORMALIZATION 0
1357: #endif