Annotation of gforth/arch/misc/misc.v, revision 1.2
1.2 ! pazsan 1: // Copyright (C) 1998,2000,2003 Free Software Foundation, Inc.
! 2:
! 3: // This file is part of Gforth.
! 4:
! 5: // Gforth is free software; you can redistribute it and/or
! 6: // modify it under the terms of the GNU General Public License
! 7: // as published by the Free Software Foundation; either version 2
! 8: // of the License, or (at your option) any later version.
! 9:
! 10: // This program is distributed in the hope that it will be useful,
! 11: // but WITHOUT ANY WARRANTY; without even the implied warranty of
! 12: // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
! 13: // GNU General Public License for more details.
! 14:
! 15: // You should have received a copy of the GNU General Public License
! 16: // along with this program; if not, write to the Free Software
! 17: // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111, USA.
! 18:
1.1 pazsan 19: /* Minimal Instruction Set Computer
20: \ sources destinations
21:
22: $0 Constant PC $0 Constant JMP
23: $1 Constant PC+2 $1 Constant JS
24: $2 Constant PC+4 $2 Constant JZ
25: $3 Constant PC+6
26: $4 Constant JC
27:
28:
29:
30: $8 Constant ACCU $8 Constant ACCU
31: $9 Constant SF $9 Constant SUB
32: $A Constant ZF $A Constant SUBR
33: $B Constant ADD
34: $C Constant CF $C Constant XOR
35: $D Constant OR
36: $E Constant AND
37: $F Constant SHR
38: */
39:
40: `define L [0:l-1]
41:
42: module misc(clock, data, addr, csel, rw);
43: parameter l=16, d=10;
44: input clock;
45: inout `L data;
46: output `L addr;
47: output csel;
48: output rw;
49:
50: reg `L inst, dtr, accu, pc;
51: reg [0:1] state;
52: reg carry, zero;
53: wire `L regs;
54: wire alusel, cout, zout, pccond;
55: wire `L alu1, alu2, aluout;
56: wire [0:2] aluop;
57:
58: initial
59: begin
60: state = 0;
61: pc = 'h10;
62: inst = 0;
63: dtr = 0;
64: accu = 0;
65: carry = 0;
66: zero = 1;
67: end
68:
69: assign
70: rw=~&state,
71: csel=~state[1] | |inst[0:l-5],
72: addr = state[1] ? inst : pc,
73: data = rw ? {l{1'bz}} : dtr;
74:
75: assign
76: alusel= inst[l-4],
77: pccond = ~|(inst[l-3:l-1] & ~{ carry, zero, accu[0] }),
78: regs = inst[l-4] ? (|inst[l-3:l-1] ? { {(l-1){1'b0}}, pccond } : accu)
79: : aluout;
80:
81: always @(posedge clock)
82: begin
83: casez(state)
84: 2'bz0 : begin
85: inst = data;
86: pc = aluout;
87: end
88: 2'b01 : begin
89: dtr = csel ? data : regs;
90: // $fwrite(2, "PC: %x : %x -( %x )->", pc-1'b1, inst, dtr);
91: end
92: 2'b11 :
93: begin
94: if(~|inst[0:l-5])
95: if(alusel) { carry, zero, accu } = { cout, zout, aluout };
96: else
97: if (pccond) pc=dtr;
98: // $fwrite(2, " %x ACCU: %x\n", inst, accu);
99: end
100: endcase /* 2 */
101: state = state + 1;
102: end
103:
104: assign
105: alu1 = &state ? accu : pc,
106: alu2 = ~state[1] ? {{l{1'b0}}, 1'b1 } :
107: state[0] ? dtr : { inst[1:l-1], 1'b0 } - 1,
108: aluop = &state ? inst[l-3:l-1] : 3'b011;
109:
110: alu #(l,d) alu0(aluop, alu1, alu2, carry, aluout, cout, zout);
111:
112: endmodule /* misc */
113:
114: module alu(op, in1, in2, cin, out, cout, zout);
115: parameter l=16, d=10;
116: input [0:2] op;
117: input `L in1, in2;
118: input cin;
119: output `L out;
120: output cout, zout;
121:
122: reg `L out;
123: reg cout;
124:
125: initial
126: cout = 0;
127:
128: always @(in1 or in2 or op)
129: #d case(op)
130: 3'b000 : { cout, out } = { cin, in2 };
131: 3'b001 : { cout, out } = in1 - in2;
132: 3'b010 : { cout, out } = in2 - in1;
133: 3'b011 : { cout, out } = in1 + in2;
134: 3'b100 : { cout, out } = { cin, in1 ^ in2 };
135: 3'b101 : { cout, out } = { cin, in1 | in2 };
136: 3'b110 : { cout, out } = { cin, in1 & in2 };
137: 3'b111 : { cout, out } = { in2[l-1], cin, in2[0:l-2] };
138: endcase /* 3 */
139:
140: assign
141: zout = ~|out;
142:
143: endmodule /* alu */
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