Annotation of gforth/arch/misc/misc.v, revision 1.1
1.1 ! pazsan 1: /* Minimal Instruction Set Computer
! 2: \ sources destinations
! 3:
! 4: $0 Constant PC $0 Constant JMP
! 5: $1 Constant PC+2 $1 Constant JS
! 6: $2 Constant PC+4 $2 Constant JZ
! 7: $3 Constant PC+6
! 8: $4 Constant JC
! 9:
! 10:
! 11:
! 12: $8 Constant ACCU $8 Constant ACCU
! 13: $9 Constant SF $9 Constant SUB
! 14: $A Constant ZF $A Constant SUBR
! 15: $B Constant ADD
! 16: $C Constant CF $C Constant XOR
! 17: $D Constant OR
! 18: $E Constant AND
! 19: $F Constant SHR
! 20: */
! 21:
! 22: `define L [0:l-1]
! 23:
! 24: module misc(clock, data, addr, csel, rw);
! 25: parameter l=16, d=10;
! 26: input clock;
! 27: inout `L data;
! 28: output `L addr;
! 29: output csel;
! 30: output rw;
! 31:
! 32: reg `L inst, dtr, accu, pc;
! 33: reg [0:1] state;
! 34: reg carry, zero;
! 35: wire `L regs;
! 36: wire alusel, cout, zout, pccond;
! 37: wire `L alu1, alu2, aluout;
! 38: wire [0:2] aluop;
! 39:
! 40: initial
! 41: begin
! 42: state = 0;
! 43: pc = 'h10;
! 44: inst = 0;
! 45: dtr = 0;
! 46: accu = 0;
! 47: carry = 0;
! 48: zero = 1;
! 49: end
! 50:
! 51: assign
! 52: rw=~&state,
! 53: csel=~state[1] | |inst[0:l-5],
! 54: addr = state[1] ? inst : pc,
! 55: data = rw ? {l{1'bz}} : dtr;
! 56:
! 57: assign
! 58: alusel= inst[l-4],
! 59: pccond = ~|(inst[l-3:l-1] & ~{ carry, zero, accu[0] }),
! 60: regs = inst[l-4] ? (|inst[l-3:l-1] ? { {(l-1){1'b0}}, pccond } : accu)
! 61: : aluout;
! 62:
! 63: always @(posedge clock)
! 64: begin
! 65: casez(state)
! 66: 2'bz0 : begin
! 67: inst = data;
! 68: pc = aluout;
! 69: end
! 70: 2'b01 : begin
! 71: dtr = csel ? data : regs;
! 72: // $fwrite(2, "PC: %x : %x -( %x )->", pc-1'b1, inst, dtr);
! 73: end
! 74: 2'b11 :
! 75: begin
! 76: if(~|inst[0:l-5])
! 77: if(alusel) { carry, zero, accu } = { cout, zout, aluout };
! 78: else
! 79: if (pccond) pc=dtr;
! 80: // $fwrite(2, " %x ACCU: %x\n", inst, accu);
! 81: end
! 82: endcase /* 2 */
! 83: state = state + 1;
! 84: end
! 85:
! 86: assign
! 87: alu1 = &state ? accu : pc,
! 88: alu2 = ~state[1] ? {{l{1'b0}}, 1'b1 } :
! 89: state[0] ? dtr : { inst[1:l-1], 1'b0 } - 1,
! 90: aluop = &state ? inst[l-3:l-1] : 3'b011;
! 91:
! 92: alu #(l,d) alu0(aluop, alu1, alu2, carry, aluout, cout, zout);
! 93:
! 94: endmodule /* misc */
! 95:
! 96: module alu(op, in1, in2, cin, out, cout, zout);
! 97: parameter l=16, d=10;
! 98: input [0:2] op;
! 99: input `L in1, in2;
! 100: input cin;
! 101: output `L out;
! 102: output cout, zout;
! 103:
! 104: reg `L out;
! 105: reg cout;
! 106:
! 107: initial
! 108: cout = 0;
! 109:
! 110: always @(in1 or in2 or op)
! 111: #d case(op)
! 112: 3'b000 : { cout, out } = { cin, in2 };
! 113: 3'b001 : { cout, out } = in1 - in2;
! 114: 3'b010 : { cout, out } = in2 - in1;
! 115: 3'b011 : { cout, out } = in1 + in2;
! 116: 3'b100 : { cout, out } = { cin, in1 ^ in2 };
! 117: 3'b101 : { cout, out } = { cin, in1 | in2 };
! 118: 3'b110 : { cout, out } = { cin, in1 & in2 };
! 119: 3'b111 : { cout, out } = { in2[l-1], cin, in2[0:l-2] };
! 120: endcase /* 3 */
! 121:
! 122: assign
! 123: zout = ~|out;
! 124:
! 125: endmodule /* alu */
FreeBSD-CVSweb <freebsd-cvsweb@FreeBSD.org>