Annotation of gforth/arch/h8/asm.fs, revision 1.1
1.1 ! pazsan 1: \ arch/h8/asm.fs assebmler for the Hitachi H8 CPU 14aug97jaw
! 2:
! 3: \ The syntax is not according to the Hitatchi reference manual.
! 4: \ Basicaly this is a forth assembler that makes heavy use of the stack.
! 5: \ The instruction must be written at last. The abstract syntax looks like:
! 6: \
! 7: \ operand:= register | address | value [ addressing-mode ]
! 8: \ instruction:= [ size-mode ] [ operand ] [ , operand ] mnemonic
! 9: \
! 10: \ All mnemonics end up with and comma, to avoid conflicts with normal
! 11: \ forth words.
! 12: \
! 13: \ E.g.:
! 14: \
! 15: \ .L $01020304 # , ER4 add,
! 16: \ $1234 jmp,
! 17: \ rts,
! 18: \
! 19: \ Addressing Modes:
! 20: \
! 21: \ The Hitachi syntax for addressing modes is very strange. Hitachis'
! 22: \ syntax says that everything with "@" gets something from memory.
! 23: \ So register indirect and memory absolute is all with "@". This is
! 24: \ easy to remember for forth-speaking people but poor in two ways:
! 25: \ "@" conflics with the forth-word, on normal CPUs there is a clear
! 26: \ syntax for "indirect" and "absolute" where it doesn't matter whether
! 27: \ we are working with a register or a memory address. This is good
! 28: \ because memory and registers could be almost the same on some CPUs,
! 29: \ or sometimes the registers are the only memory we have.
! 30: \ On some CPUs we could simply replace the register-label by a
! 31: \ memory-label when we are out of registers (works not for the H8 and
! 32: \ RISCs because absolute addressing only works in MOV)
! 33:
! 34: \ Addressing Mode H8 H-Symbol F-Symbol
! 35: \ Register direct R0 R0
! 36: \ Register indirect @ER0 ER0 ]
! 37: \ Register indirect with displ @(0,ER0) ER0 0 #]
! 38: \ Register ind. post increment @ER0+ ER0 ]+
! 39: \ Register ind. pre decrement @-ER0 ER0 -]
! 40: \ Absolute address @01234 01234
! 41: \ PC relative @(0,PC) PC 0 #]
! 42: \ Memory indirect @@12 12 ]
! 43:
! 44: include asm/generic.fs
! 45: include asm/bitmask.fs
! 46:
! 47: hex
! 48:
! 49: -1 ByteDirection !
! 50:
! 51: \ Bytes
! 52:
! 53: : 22! ( c -- ) I-Latch 1 chars + c! ;
! 54: : 34! ( word -- ) I-Latch 2 chars + 2 g! ;
! 55: : 36! ( quad -- ) I-Latch 2 chars + 4 g! ;
! 56:
! 57: \ Nibles r= right l= left
! 58:
! 59: : 1nr! I-Latch c@ maskinto $0F I-Latch c! ;
! 60: : 2nr! I-Latch char+ c@ maskinto $0F I-Latch char+ c! ;
! 61: : 2nl! I-Latch char+ c@ maskinto $F0 I-Latch char+ c! ;
! 62: : 4nr! I-Latch 4 chars + c@ maskinto %00001111 I-Latch 4 chars + c! ;
! 63: : 4nl! I-Latch 4 chars + c@ maskinto %11110000 I-Latch 4 chars + c! ;
! 64:
! 65: \ Small Nibles
! 66:
! 67: : 2sr! I-Latch char+ c@ maskinto %00000111 I-Latch char+ c! ;
! 68: : 2sl! I-Latch char+ c@ maskinto %01110000 I-Latch char+ c! ;
! 69: : 4sr! I-Latch 4 chars + c@ maskinto %00000111 I-Latch 4 chars + c! ;
! 70: : 4sl! I-Latch 4 chars + c@ maskinto %01110000 I-Latch 4 chars + c! ;
! 71:
! 72: \ ----- Addressing Modes
! 73:
! 74: 1 0Mode .B
! 75: 2 0Mode .W
! 76: 3 0Mode .L
! 77:
! 78: 01 Mode 8Reg
! 79: 02 Mode 16Reg
! 80: 03 Mode 32Reg
! 81:
! 82: 10 Mode # \ Immediate
! 83: 20 Mode ] \ Register/Memory indirect
! 84: 30 Mode #] \ Register indirect with displacement
! 85: \ room for long displacement
! 86: 50 Mode ]+ \ Register indirect with post increment
! 87: 60 Mode -] \ Register indirect with pre decrement
! 88:
! 89: 100 Mode PC \ Program counter ( used together with #] )
! 90:
! 91: a0 Mode #1
! 92: b0 Mode #2
! 93: c0 Mode #4
! 94:
! 95: \ Registers
! 96:
! 97: : R: ['] 16Reg Reg ;
! 98: : ER: ['] 32Reg Reg ;
! 99:
! 100: 0 R: R0
! 101: 1 R: R1
! 102: 2 R: R2
! 103: 3 R: R3
! 104: 4 R: R4
! 105: 5 R: R5
! 106: 6 R: R6
! 107: 7 R: R7
! 108:
! 109: \ ... ?
! 110:
! 111: 0 ER: ER0
! 112: 1 ER: ER1
! 113: 2 ER: ER2
! 114: 3 ER: ER3
! 115: 4 ER: ER4
! 116:
! 117: \ ... ?
! 118:
! 119: : i8,r 22! 1nr! ;
! 120: : r,r 2nr! 2nl! ;
! 121: : i16,r 2nr! 34! ;
! 122: : er,er 2sr! 2sl! ;
! 123: : er,er4 4sr! 4sl! ;
! 124: : i32,er BREAK: 2sr! 36! ;
! 125: : ,er 2sr! ;
! 126: : abs24 I-Latch char+ 3 g! ;
! 127: : abs8 I-Latch char+ c! ;
! 128: : ,r 2nr! ;
! 129:
! 130: Table add,
! 131: .B # , R0 ' i8,r opc( 80 00
! 132: .B R0 , R0 ' r,r opc( 08 00
! 133: .W # , R0 ' i16,r opc( 79 10 00 00
! 134: .W R0 , R0 ' r,r opc( 09 00
! 135: .L # , ER0 ' i32,er opc( 7A 10 00 00 00 00
! 136: .L ER0 , ER0 ' er,er opc( 0A 80
! 137: End-Table
! 138:
! 139: Table adds,
! 140: #1 , ER0 ' ,er opc( 0B 00
! 141: #2 , ER0 ' ,er opc( 0B 80
! 142: #4 , ER0 ' ,er opc( 0B 90
! 143: End-Table
! 144:
! 145: Table subs, opc+ 10
! 146: Follows adds,
! 147:
! 148: Table jmp,
! 149: ER0 ] ' ,er opc( 59 00
! 150: 0 ' abs24 opc( 5A 00 00
! 151: 0 ] ' abs8 opc( 5B 00
! 152: End-Table
! 153:
! 154: Table jsr, opc+ 04
! 155: Follows jmp,
! 156:
! 157: Table inc,
! 158: .B R0 ' ,r opc( 0A 00
! 159: .W #1 , R0 ' ,r opc( 0B 50
! 160: .W #2 , R0 ' ,r opc( 0B D0
! 161: .L #1 , ER0 ' ,r opc( 0B 70
! 162: .L #2 , ER0 ' ,r opc( 0B F0
! 163: End-Table
! 164:
! 165: Table dec, opc+ 10
! 166: Follows inc,
! 167:
! 168: Alone sleep, 01 80
! 169: Alone rts, 54 70
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