| @article{Hoare, |
@article{Hoare03, |
| author = {Tony Hoare}, |
author = {Tony Hoare}, |
| title = {The verifying compiler: A grand challenge for computing research}, |
title = {The verifying compiler: A grand challenge for computing research}, |
| journal = {Journal of the ACM}, |
journal = {Journal of the ACM}, |
| address = {New York, NY, USA}, |
address = {New York, NY, USA}, |
| } |
} |
| |
|
| @article{1328444, |
@inproceedings{TristanLeroy09, |
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author = {Jean-Baptiste Tristan and Xavier Leroy}, |
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title = {Verified Validation of Lazy Code Motion}, |
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booktitle = {PLDI '09: Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation}, |
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year = {2009}, |
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isbn = {978-1-60558-392-1}, |
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pages = {316--326}, |
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location = {Dublin, Ireland}, |
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doi = {http://doi.acm.org/10.1145/1542476.1542512}, |
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publisher = {ACM}, |
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address = {New York, NY, USA}, |
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} |
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|
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@inproceedings{Kundu+09, |
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author = {Sudipta Kundu and Zachary Tatlock and Sorin Lerner}, |
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title = {Proving Optimizations Correct using Parameterized Program Equivalence}, |
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booktitle = {PLDI '09: Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation}, |
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year = {2009}, |
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isbn = {978-1-60558-392-1}, |
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pages = {327--337}, |
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location = {Dublin, Ireland}, |
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doi = {http://doi.acm.org/10.1145/1542476.1542513}, |
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publisher = {ACM}, |
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address = {New York, NY, USA}, |
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} |
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|
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@inproceedings{Necula00, |
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author = {George C. Necula}, |
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title = {Translation Validation for an Optimizing Compiler}, |
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booktitle = {PLDI '00: Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation}, |
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year = {2000}, |
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isbn = {1-58113-199-2}, |
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pages = {83--94}, |
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location = {Vancouver, British Columbia, Canada}, |
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doi = {http://doi.acm.org/10.1145/349299.349314}, |
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publisher = {ACM}, |
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address = {New York, NY, USA}, |
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} |
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|
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@article{TristanLeroy08, |
| author = {Jean-Baptiste Tristan and Xavier Leroy}, |
author = {Jean-Baptiste Tristan and Xavier Leroy}, |
| title = {Formal verification of translation validators: a case study on instruction scheduling optimizations}, |
title = {Formal verification of translation validators: a case study on instruction scheduling optimizations}, |
| journal = {SIGPLAN Not.}, |
journal = {SIGPLAN Not.}, |
| address = {New York, NY, USA}, |
address = {New York, NY, USA}, |
| } |
} |
| |
|
| @article{1314860, |
@inproceedings{ZaksPnueli08, |
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author = {Anna Zaks and Amir Pnueli}, |
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title = {Program Analysis for Compiler Validation}, |
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booktitle = {PASTE '08: Proceedings of the 8th ACM SIGPLAN-SIGSOFT workshop on Program analysis for software tools and engineering}, |
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year = {2008}, |
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isbn = {978-1-60558-382-2}, |
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pages = {1--7}, |
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location = {Atlanta, Georgia}, |
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doi = {http://doi.acm.org/10.1145/1512475.1512477}, |
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publisher = {ACM}, |
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address = {New York, NY, USA}, |
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} |
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|
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@inproceedings{Pnueli98b, |
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author = {Amir Pnueli and Michael Siegel and Eli Singerman}, |
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title = {Translation Validation}, |
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booktitle = {TACAS '98: Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems}, |
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year = {1998}, |
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isbn = {3-540-64356-7}, |
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pages = {151--166}, |
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publisher = {Springer-Verlag}, |
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address = {London, UK}, |
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} |
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|
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@Article{Pnueli98a, |
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author = "Amir Pnueli and Ofer Shtrichman and Michael Siegel", |
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title = "The {Code Validation Tool (CVT)}: Automatic |
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verification of a compilation process", |
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journal = "International Journal on Software Tools for Technology |
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Transfer (STTT)", |
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volume = "2", |
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number = "2", |
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pages = "192--201", |
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month = "December", |
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year = "1998", |
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ISSN = "1433-2779 (print), 1433-2787 (electronic)", |
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} |
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|
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@article{GlesnerGoosZimmeermann04, |
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author = {Sabine Glesner and |
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Gerhard Goos and |
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Wolf Zimmermann}, |
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title = {Verifix: Konstruktion und Architektur verifizierender {\"U}bersetzer |
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(Verifix: Construction and Architecture of Verifying Compilers)}, |
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journal = {it - Information Technology}, |
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volume = {46}, |
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number = {5}, |
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year = {2004}, |
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pages = {265-276}, |
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ee = {http://dx.doi.org/10.1524/itit.46.5.265.44799}, |
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bibsource = {DBLP, http://dblp.uni-trier.de} |
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} |
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|
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@inproceedings{GoosZimmermann00, |
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author = {Gerhard Goos and Wolf Zimmermann}, |
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title = {Verifying Compilers and ASMs}, |
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booktitle = {Abstract State Machines}, |
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editor = {Yuri Gurevich and |
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Philipp W. Kutter and |
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Martin Odersky and |
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Lothar Thiele}, |
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year = {2000}, |
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pages = {177-202}, |
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publisher = {Springer}, |
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series = {Lecture Notes in Computer Science}, |
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volume = {1912}, |
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} |
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|
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@article{BlechPoetzsch07, |
| author = {Jan Olaf Blech and Arnd Poetzsch-Heffter}, |
author = {Jan Olaf Blech and Arnd Poetzsch-Heffter}, |
| title = {A Certifying Code Generation Phase}, |
title = {A Certifying Code Generation Phase}, |
| journal = {Electron. Notes Theor. Comput. Sci.}, |
journal = {Electron. Notes Theor. Comput. Sci.}, |
| address = {New York, NY, USA}, |
address = {New York, NY, USA}, |
| } |
} |
| |
|
| |
@ARTICLE{Oh+02a, |
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title={Error detection by duplicated instructions in super-scalar processors}, |
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author={Oh, N. and Shirvani, P.P. and McCluskey, E.J.}, |
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journal={Reliability, IEEE Transactions on}, |
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year={2002}, |
| |
month={Mar}, |
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volume={51}, |
| |
number={1}, |
| |
pages={63-75}, |
| |
keywords={error detection, instruction sets, parallel architectures, software fault tolerance, software reliabilityconcurrent error detection, error detection by duplicated instructions, error-detection coverage, error-detection coverage estimation, execution time overhead, fault tolerance, fault-coverage, instruction-level parallelism, instruction-scheduling, instructions duplication, memory code segment fault, performance overhead reduction, probabilistic methods, registers, single event upset, software technique, super-scalar processors, system operation, transient fault}, |
| |
doi={10.1109/24.994913}, |
| |
ISSN={0018-9529}, } |
| |
|
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@ARTICLE{Oh+02b, |
| |
title={Control-flow checking by software signatures}, |
| |
author={Oh, N. and Shirvani, P.P. and McCluskey, E.J.}, |
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journal={Reliability, IEEE Transactions on}, |
| |
year={2002}, |
| |
month={Mar}, |
| |
volume={51}, |
| |
number={1}, |
| |
pages={111-122}, |
| |
keywords={program diagnostics, program testing, software reliabilityassigned signatures, branching fault injection experiment, branching faults, code size reduction, compilation time, control flow checking by software signatures, error detection instructions, execution time overhead reduction, instructions checking, multitasking environment, program graph, run-time signatures, signature monitoring techniques, software method, undetected incorrect outputs, watchdog task}, |
| |
doi={10.1109/24.994926}, |
| |
ISSN={0018-9529}, } |
| |
|
| |
@ARTICLE{Oh+02c, |
| |
title={Error detection by selective procedure call duplication for low energy consumption}, |
| |
author={Nahmshuk Oh, Nahmshuk and Edward J. McCluskey}, |
| |
journal={IEEE Transactions onReliability}, |
| |
year={2002}, |
| |
month={Dec}, |
| |
volume={51}, |
| |
number={4}, |
| |
pages={ 392-402}, |
| |
keywords={ error detection, fault tolerant computing, power consumption, software fault tolerance commercial off-the-shelf components, data integrity, energy consumption reduction, error detection, error-detection latency, error-detection overhead minimisation, fault tolerance, hardware fault-tolerant techniques, instruction duplication, low energy consumption, low energy technique, low power technique, procedure cloning, selective procedure call duplication, software error detection, system reliability improvement, system-on-chip design technique, transient errors detection}, |
| |
doi={10.1109/TR.2002.804735}, |
| |
ISSN={0018-9529}, } |
| |
|
| @BOOK{MishraDutt08, |
@BOOK{MishraDutt08, |
| TITLE = {Processor Description Languages}, |
TITLE = {Processor Description Languages}, |
| AUTHOR = {Prabhat Mishra and Nikil Dutt (Editor)}, |
AUTHOR = {Prabhat Mishra and Nikil Dutt (Editor)}, |
| YEAR = {2008}, |
YEAR = {2008}, |
| } |
} |
| |
|
| |
@InProceedings{BrooksTiwariMartonosi00, |
| |
author = "David Brooks and Vivek Tiwari and Margaret Martonosi", |
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title = "Wattch: {A} Framework for Architectural-Level Power |
| |
Analysis and Optimizations", |
| |
booktitle = "Proceedings of the 27th Annual International Symposium |
| |
on Computer Architecture", |
| |
location = "Vancouver, British Columbia", |
| |
organization = "IEEE Computer Society and ACM SIGARCH", |
| |
month = "June" # " 12--14,", |
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year = "2000", |
| |
pages = "83--94", |
| |
} |
| |
|
| |
|
| @InProceedings{SchrSchoKn09, |
@InProceedings{SchrSchoKn09, |
| TITLE = "Adding Timing-Awareness to {AUTOSAR} Basic-Software - A Component Based Approach", |
TITLE = "Adding Timing-Awareness to {AUTOSAR} Basic-Software - A Component Based Approach", |
| AUTHOR = "Dietmar Schreiner and Markus Schordan and Jens Knoop", |
AUTHOR = "Dietmar Schreiner and Markus Schordan and Jens Knoop", |
| MONTH = {January}, |
MONTH = {January}, |
| YEAR = {2009}, |
YEAR = {2009}, |
| } |
} |
| |
|
| |
@INCOLLECTION{BrHoKr09, |
| |
AUTHOR = {Florian Brandner and Nigel Horspool and Andreas Krall}, |
| |
EDITOR = {Shuvra S. Bhattacharyya and Ed Deprettere and Rainer Leupers and Jarmo Takala}, |
| |
BOOKTITLE = {Handbook on Signal Processing Systems}, |
| |
TITLE = {DSP Instruction Set Simulation}, |
| |
PUBLISHER = {Springer}, |
| |
PAGES = {to appear}, |
| |
MONTH = {December}, |
| |
YEAR = {2009} |
| |
} |
| |
|