| |
|
| / ( n1 n2 -- n ) core slash |
/ ( n1 n2 -- n ) core slash |
| n = n1/n2; |
n = n1/n2; |
| if(FLOORED_DIV && (n1 < 0) != (n2 < 0) && (n1%n2 != 0)) n--; |
if(FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) n--; |
| : |
: |
| /mod nip ; |
/mod nip ; |
| |
|
| mod ( n1 n2 -- n ) core |
mod ( n1 n2 -- n ) core |
| n = n1%n2; |
n = n1%n2; |
| if(FLOORED_DIV && (n1 < 0) != (n2 < 0) && n!=0) n += n2; |
if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) n += n2; |
| : |
: |
| /mod drop ; |
/mod drop ; |
| |
|
| /mod ( n1 n2 -- n3 n4 ) core slash_mod |
/mod ( n1 n2 -- n3 n4 ) core slash_mod |
| n4 = n1/n2; |
n4 = n1/n2; |
| n3 = n1%n2; /* !! is this correct? look into C standard! */ |
n3 = n1%n2; /* !! is this correct? look into C standard! */ |
| if (FLOORED_DIV && (n1<0) != (n2<0) && n3!=0) { |
if (FLOORED_DIV && ((n1^n2) < 0) && n3!=0) { |
| n4--; |
n4--; |
| n3+=n2; |
n3+=n2; |
| } |
} |
| /* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
| n5 = d/n3; |
n5 = d/n3; |
| n4 = d%n3; |
n4 = d%n3; |
| if (FLOORED_DIV && (d<0) != (n3<0) && n4!=0) { |
if (FLOORED_DIV && ((DHI(d)^n3)<0) && n4!=0) { |
| n5--; |
n5--; |
| n4+=n3; |
n4+=n3; |
| } |
} |
| #else |
#else |
| /* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
| n4 = d/n3; |
n4 = d/n3; |
| if (FLOORED_DIV && (d<0) != (n3<0) && (d%n3)!=0) n4--; |
if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) n4--; |
| #endif |
#endif |
| : |
: |
| */mod nip ; |
*/mod nip ; |
| #ifdef BUGGY_LL_DIV |
#ifdef BUGGY_LL_DIV |
| #ifdef ASM_SM_SLASH_REM |
#ifdef ASM_SM_SLASH_REM |
| ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
| if ((d1.hi<0) != (n1<0) && n2!=0) { |
if (((DHI(d1)^n1)<0) && n2!=0) { |
| n3--; |
n3--; |
| n2+=n1; |
n2+=n1; |
| } |
} |
| #else |
#else |
| #ifdef ASM_SM_SLASH_REM4 |
#ifdef ASM_SM_SLASH_REM4 |
| ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
| if ((d1<0) != (n1<0) && n2!=0) { |
if (((DHI(d1)^n1)<0) && n2!=0) { |
| n3--; |
n3--; |
| n2+=n1; |
n2+=n1; |
| } |
} |
| n3 = d1/n1; |
n3 = d1/n1; |
| n2 = d1%n1; |
n2 = d1%n1; |
| /* note that this 1%-3>0 is optimized by the compiler */ |
/* note that this 1%-3>0 is optimized by the compiler */ |
| if (1%-3>0 && (d1<0) != (n1<0) && n2!=0) { |
if (1%-3>0 && ((DHI(d1)^n1)<0) && n2!=0) { |
| n3--; |
n3--; |
| n2+=n1; |
n2+=n1; |
| } |
} |
| n3 = d1/n1; |
n3 = d1/n1; |
| n2 = d1%n1; |
n2 = d1%n1; |
| /* note that this 1%-3<0 is optimized by the compiler */ |
/* note that this 1%-3<0 is optimized by the compiler */ |
| if (1%-3<0 && (d1<0) != (n1<0) && n2!=0) { |
if (1%-3<0 && ((DHI(d1)^n1)<0) && n2!=0) { |
| n3++; |
n3++; |
| n2-=n1; |
n2-=n1; |
| } |
} |