| n3=DLO(r); |
n3=DLO(r); |
| #endif /* !defined(ASM_SM_SLASH_REM) */ |
#endif /* !defined(ASM_SM_SLASH_REM) */ |
| #else |
#else |
| |
#ifdef ASM_SM_SLASH_REM4 |
| |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
| |
if ((d1<0) != (n1<0) && n2!=0) { |
| |
n3--; |
| |
n2+=n1; |
| |
} |
| |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
| /* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
| n3 = d1/n1; |
n3 = d1/n1; |
| n2 = d1%n1; |
n2 = d1%n1; |
| n3--; |
n3--; |
| n2+=n1; |
n2+=n1; |
| } |
} |
| |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
| #endif |
#endif |
| : |
: |
| dup >r dup 0< IF negate >r dnegate r> THEN |
dup >r dup 0< IF negate >r dnegate r> THEN |
| n3=DLO(r); |
n3=DLO(r); |
| #endif /* !defined(ASM_SM_SLASH_REM) */ |
#endif /* !defined(ASM_SM_SLASH_REM) */ |
| #else |
#else |
| |
#ifdef ASM_SM_SLASH_REM4 |
| |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
| |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
| /* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
| n3 = d1/n1; |
n3 = d1/n1; |
| n2 = d1%n1; |
n2 = d1%n1; |
| n3++; |
n3++; |
| n2-=n1; |
n2-=n1; |
| } |
} |
| |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
| #endif |
#endif |
| : |
: |
| over >r dup >r abs -rot |
over >r dup >r abs -rot |
| u3=DLO(r); |
u3=DLO(r); |
| #endif /* !defined(ASM_UM_SLASH_MOD) */ |
#endif /* !defined(ASM_UM_SLASH_MOD) */ |
| #else |
#else |
| |
#ifdef ASM_UM_SLASH_MOD4 |
| |
ASM_UM_SLASH_MOD4(d1, n1, n2, n3); |
| |
#else /* !defined(ASM_UM_SLASH_MOD4) */ |
| u3 = ud/u1; |
u3 = ud/u1; |
| u2 = ud%u1; |
u2 = ud%u1; |
| |
#endif /* !defined(ASM_UM_SLASH_MOD4) */ |
| #endif |
#endif |
| : |
: |
| 0 swap [ 8 cells 1 + ] literal 0 |
0 swap [ 8 cells 1 + ] literal 0 |