Timing Predictability and Composability

Peter Puschner and Raimund Kirner

Vienna University of Technology, Vienna, Austria

As real-time software is increasing in size and complexity, the need for advanced modeling and analysis capabilities early in the software development process is getting more and more urgent. One particular concern is the lack of sufficient methods and tools to effectively reason about the timing of software in such a way that software systems can be constructed hierarchically from components while still guaranteeing the timing properties [1]. In this talk, we will discuss deficiencies in current real-time embedded hardware and software structures with respect to achieving our goal of composable and compositional timing behavior. To address these deficiencies, we will then discuss programming methods, code generation techniques, and ideas about hardware and software architectures that should help us in achieving a truly timing-composable and compositional engineering process for real-time software systems.

(Parts of the research leading to these results have received funding from the European Community's Seventh Framework Programme [FP7/2007-2013] under grant agreement no. 214373.)  


[1]     Peter Puschner, Raimund Kirner, and Robert G. Pettit. Towards Composable Timing for Real-Time Software. In Proc. 1st International Workshop on Software Technologies for Future Dependable Distributed Systems, pages 1-5. IEEE Computer Society CPS, Mar. 2009.


Peter Puschner is a professor in computer science at Vienna University of Technology. His main research interest is on hard real-time systems for safety-critical applications, with a focus on the worst-case execution time (WCET) analysis of real-time programs and software/hardware architectures for time-predictable computing. He has published more than 80 refereed conference and journal papers and was a guest editor for the special issue on WCET analysis of the Kluwer (now Springer) International Journal on Real-Time Systems in 2000. P. Puschner chaired the PC of ISORC 2003 and ECRST 2004 and was the general chair of the Euromicro Conference on Real-Time Systems 2002 and ISORC 2004. He is in charge of the steering committees of the workshop series on worst-case execution-time analysis (WCET) and the International Workshop on Software Technologies for Future Embedded and Ubiquitous Computing Systems (SEUS). P. Puschner is a member of the IEEE Computer Society, IFIP working group 10.2 on Embedded Systems, Euromicro, the OCG (Austrian Computer Society), and the Marie-Curie Fellowship Association.

Univ. Assistent Dr. Raimund Kirner received his Master's degree and his PhD degree at the Vienna University of Technology (TU Vienna) in 2000 respectively 2003. During this time he has been working as a research and teaching assistant at the Institut für Technische Informatik at TU Vienna. The main focus of Kirner's research is worst-case execution time analysis of real-time programs, including compiler support and design methodologies to make systems predictable. He has published several papers on WCET analysis and was involved in two projects funded by the European Commission (SETTA, NEXT TTA). From 2003-2005 Raimund Kirner has worked on the FIT-IT project MoDECS, and from 2005-2007 he worked on the FIT-IT project TeDES, both funded by the Federal Ministry of Transport, Innovation, and Technology (BMVIT). Currently, Raimund Kirner is principal investigator of the following projects: "Compiler-Support for Timing Analysis" (COSTA), "Formal Timing Analysis Suite" (FORTAS), and "Sustaining Entire Code-Coverage on Code Optimization" (SECCO). He is a member of the IEEE Computer Society, the ACM, and the Austrian Computer Society (OCG).

Contact Peter and Raimund at:

Prof. Peter Puschner
Institute of Computer Engineering
Vienna University of Technology
A-1040 Vienna, Austria
peter at vmars.tuwien.ac.at

Dr. Raimund Kirner
Institute of Computer Engineering
Vienna University of Technology
A-1040 Vienna, Austria
raimund at vmars.tuwien.ac.at