Seminar mit Bakkalaureatsarbeit LVA 185.188, SE 3.0, 2005 S
und
Wissenschaftliches Arbeiten
LVA 185.217 SE 2.0, 2005 S
| Nr. | Titel |
|---|---|
| 1 | Robert D. Arnold, Frank Mueller, David Whalley, and Marion Harmon. Bounding Worst-Case Instruction Cache Performance. In Proc. 15th Real-Time Systems Symposium (RTSS), pages 172 - 181, Brookline, Massachusetts, Dec. 1994. |
| 2 | Jakob Engblom, Andreas Ermedahl, and Peter Altenbernd. Facilitating Worst-Case Execution Time Analysis for Optimized Code. In Proc. 10th Euromicro Real-Time Workshop, Berlin, Germany, June 1998. |
| 3 | Jakob Engblom and Bengt Jonsson. Processor pipelines and their properties for static wcet analysis. In Proc. 2nd Embedded Software Conference, Grenoble, France, Oct. 2002. LNCS 2491, Springer Verlag. |
| 4 | Christian Ferdinand, Reinhold Heckmann, Marc Langenbach, Florian Martin, Michael Schmidt, Henrik Theiling, Stephan Thesing, and Reinhard Wilhelm. Reliable and precise wcet determination for a real-life processor. In Proc. of the 1st International Workshop on Embedded Software (EMSOFT 2001), pages 469 - 485, Tahoe City, CA, USA, Oct. 2001. |
| 5 | Jan Gustafsson and Andreas Ermedahl. Automatic derivation of path and loop annotations in object-oriented real-time programs. Parallel and Distributed Computing Practices, 1(2), June 1998. |
| 6 | Christopher A. Healy, Robert D. Arnold, Frank Mueller, David Whalley, and Marion G. Harmon. Bounding Pipeline and Instruction Cache Performance. IEEE Transactions on Computers, 48(1), Jan. 1999. |
| 7 | Reinhold Heckmann, Marc Langenbach, Stephan Thesing, and Reinhard Wilhelm. The influence of processor architecture on the design and results of wcet tools. Proceedings of the IEEE, 91(7):1038-1054, Jul. 2003. |
| 8 | Christopher A. Healy, Mikael Sjödin, and David B. Whalley. Bounding Loop Iterations for Timing Analysis. In Proc. IEEE Real-Time Technology and Aplications Symposium, pages 12 - 21, June 1998. |
| 9 | Christopher A. Healy, David B. Whalley, and Marion G. Harmon. Integrating the timing analysis of pipelining and instruction caching. In Proc. 16th IEEE Real-Time Systems Symposium (RTSS), pages 288 - 297, Los Alamitos, California, 1995. IEEE CS Press. |
| 10 | Hung-ju Lee Jyh-Charn Liu. Deterministic upperbounds of the worstcase execution times of cached programs. In Proc. 15th IEEE Real-Time Systems Symposium, pages 182 191, San Juan, Puerto Rico, Dec. 1994. IEEE Computer Society. |
| 11 | Clara I. Jaramillo, Rajiv Gupta, and Mary L. Soffa. Capturing the Effects of Code Improving Transformations. In Proc. International Conference on Parallel Architectures and Compilation Techniques (PACT 98), pages 118 - 123, Paris, France, Oct. 1998. |
| 12 | Raimund Kirner and Peter Puschner. Timing analysis of optimised code. In Proc. 8th IEEE International Workshop on Objectoriented Real-time Dependable Systems (WORDS 2003), pages 100 - 105, Guadalajara, Mexico, Jan. 2003. |
| 13 | Raimund Kirner and Peter Puschner. Transformation of metainformation by abstract co-interpretation. In Proc. 7th International Workshop on Software and Compilers for Embedded Systems, pages 298 - 312, Vienna, Austria, Sep. 2003. |
| 14 | Raimund Kirner, Peter Puschner, and Ingomar Wenzel. Measurementbased worst-case execution time analysis using automatic test-data generation. In Proc. 4th Euromicro International Workshop on WCET Analysis, pages 67 - 70, Catania, Italy, June 2004. |
| 15 | Sung-Soo Lim, Young H. Bae, Gyu T. Jang, Byung-Do Rhee, Sang L. Min, Chang Y. Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, and Chong-Sang Kim. An accurate worst case timing analysis for RISC processors. Software Engineering, 21(7):593-604, 1995. |
| 16 | Sung-Soo Lim, Jihong Kim, and Sang L. Min. A worst case timing analysis technique for optimized programs. In Proc. 5th International Conference on Real-Time Computing Systems and Applications (RTCSA), pages 151 - 157, Hiroshima, Japan, Oct. 1998. |
| 17 | Yau-Tsun Steven Li, Sharad Malik, and Andrew Wolfe. E±cient Microarchitecture Modeling and Path Analysis for Real-Time Software. In Proc. IEEE Real-Time Systems Symposium, pages 298 - 307, Dec. 1995. |
| 18 | Yau-Tsun Steven Li, Sharad Malik, and Andrew Wolfe. Performance Estimation of Embedded Software with Instruction Cache Modeling. In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 380 - 387, Nov. 1995. |
| 19 | Aloysius K. Mok, Prasanna Amerasinghe, Moyer Chen, and Kamtorn Tantisirivat. Evaluating Tight Execution Time Bounds of Programs by Annotations. In Proc. 6th IEEE Worksop on Real-Time Operating Systems and Software, pages 74 - 80, Pittsburgh, PA, USA, May 1989. |
| 20 | Chang Y. Park and Alan C. Shaw. Experiments with a Program Timing Tool based on a Source-Level Timing Schema. Computer, 24(5):48-57, May 1991. |
| 21 | Alexander Vrchoticky. Compilation Support for Fine-Grained Execution Time Analysis. In Proc. ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, Orlando FL, June 1994. |
| 22 | Thomas Lundqvist and Per Stenström. Timing analysis in dynamically scheduled microprocessors. In Proc. 20th IEEE Real-Time Systems Symposium (RTSS), pages 12 - 21, Dec. 1999. |
| 23 | Frank Mueller. Generalizing Timing Predictions to Set-Associative Caches. In Workshop on Real-Time Systems, pages 64 - 71, June 1997. |
| 24 | Stefan M. Petters and Georg Färber. Making worst case execution time analysis for hard real-time tasks on state of the art processors feasible. In Proc. 6th Int. Conf. on Real-Time Computing Systems and Applications (RTCSA 99), Hongkong, ROC, Dec. 1999. IEEE Computer Society Press. |
| 25 | Chang Y. Park. Predicting Program Execution Times by Analyzing Static and Dynamic Program Paths. Real-Time Systems, 5(1):31-62, 1993. |