--- gforth/prim 2006/10/13 17:15:27 1.196 +++ gforth/prim 2006/10/30 15:29:48 1.201 @@ -809,12 +809,21 @@ n = n1*n2; / ( n1 n2 -- n ) core slash n = n1/n2; -if(FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) n--; +if (CHECK_DIVISION_SW && n2 == 0) + throw(BALL_DIVZERO); +if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) + throw(BALL_RESULTRANGE); +if (FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) + n--; : /mod nip ; mod ( n1 n2 -- n ) core n = n1%n2; +if (CHECK_DIVISION_SW && n2 == 0) + throw(BALL_DIVZERO); +if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) + throw(BALL_RESULTRANGE); if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) n += n2; : /mod drop ; @@ -822,6 +831,10 @@ if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) /mod ( n1 n2 -- n3 n4 ) core slash_mod n4 = n1/n2; n3 = n1%n2; /* !! is this correct? look into C standard! */ +if (CHECK_DIVISION_SW && n2 == 0) + throw(BALL_DIVZERO); +if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) + throw(BALL_RESULTRANGE); if (FLOORED_DIV && ((n1^n2) < 0) && n3!=0) { n4--; n3+=n2; @@ -842,12 +855,17 @@ n4=DHI(r); n5=DLO(r); #else /* assumes that the processor uses either floored or symmetric division */ -n5 = d/n3; +DCell d5 = d/n3; n4 = d%n3; +if (CHECK_DIVISION_SW && n3 == 0) + throw(BALL_DIVZERO); if (FLOORED_DIV && ((DHI(d)^n3)<0) && n4!=0) { - n5--; + d5--; n4+=n3; } +n5 = d5; +if (CHECK_DIVISION && d5 != n5) + throw(BALL_RESULTRANGE); #endif : >r m* r> fm/mod ; @@ -864,8 +882,14 @@ DCell r = fmdiv(d,n3); n4=DLO(r); #else /* assumes that the processor uses either floored or symmetric division */ -n4 = d/n3; -if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) n4--; +DCell d4 = d/n3; +if (CHECK_DIVISION_SW && n3 == 0) + throw(BALL_DIVZERO); +if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) + d4--; +n4 = d4; +if (CHECK_DIVISION && d4 != n4) + throw(BALL_RESULTRANGE); #endif : */mod nip ; @@ -889,36 +913,29 @@ n2 = n1>>1; fm/mod ( d1 n1 -- n2 n3 ) core f_m_slash_mod ""Floored division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, @i{n1}>@i{n2}>=0 or 0>=@i{n2}>@i{n1}."" -#ifdef BUGGY_LL_DIV #ifdef ASM_SM_SLASH_REM +#ifdef BUGGY_LL_DIV ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); if (((DHI(d1)^n1)<0) && n2!=0) { + if (CHECK_DIVISION && n3 == CELL_MIN) + throw(BALL_RESULTRANGE); n3--; n2+=n1; } -#else /* !defined(ASM_SM_SLASH_REM) */ -DCell r = fmdiv(d1,n1); -n2=DHI(r); -n3=DLO(r); -#endif /* !defined(ASM_SM_SLASH_REM) */ #else -#ifdef ASM_SM_SLASH_REM4 ASM_SM_SLASH_REM4(d1, n1, n2, n3); if (((DHI(d1)^n1)<0) && n2!=0) { + if (CHECK_DIVISION && n3 == CELL_MIN) + throw(BALL_RESULTRANGE); n3--; n2+=n1; } -#else /* !defined(ASM_SM_SLASH_REM4) */ -/* assumes that the processor uses either floored or symmetric division */ -n3 = d1/n1; -n2 = d1%n1; -/* note that this 1%-3>0 is optimized by the compiler */ -if (1%-3>0 && ((DHI(d1)^n1)<0) && n2!=0) { - n3--; - n2+=n1; -} -#endif /* !defined(ASM_SM_SLASH_REM4) */ #endif +#else /* !defined(ASM_SM_SLASH_REM) */ +DCell r = fmdiv(d1,n1); +n2=DHI(r); +n3=DLO(r); +#endif /* !defined(ADM_SM_SLASH_REM) */ : dup >r dup 0< IF negate >r dnegate r> THEN over 0< IF tuck + swap THEN @@ -940,13 +957,18 @@ n3=DLO(r); ASM_SM_SLASH_REM4(d1, n1, n2, n3); #else /* !defined(ASM_SM_SLASH_REM4) */ /* assumes that the processor uses either floored or symmetric division */ -n3 = d1/n1; +DCell d3 = d1/n1; n2 = d1%n1; +if (CHECK_DIVISION_SW && n1 == 0) + throw(BALL_DIVZERO); /* note that this 1%-3<0 is optimized by the compiler */ if (1%-3<0 && ((DHI(d1)^n1)<0) && n2!=0) { - n3++; + d3++; n2-=n1; } +n3 = d3; +if (CHECK_DIVISION && d3 != n3) + throw(BALL_RESULTRANGE); #endif /* !defined(ASM_SM_SLASH_REM4) */ #endif : @@ -996,8 +1018,13 @@ u3=DLO(r); #ifdef ASM_UM_SLASH_MOD4 ASM_UM_SLASH_MOD4(ud, u1, u2, u3); #else /* !defined(ASM_UM_SLASH_MOD4) */ -u3 = ud/u1; +UDCell ud3 = ud/u1; u2 = ud%u1; +if (CHECK_DIVISION_SW && u1 == 0) + throw(BALL_DIVZERO); +u3 = ud3; +if (CHECK_DIVISION && ud3 != u3) + throw(BALL_RESULTRANGE); #endif /* !defined(ASM_UM_SLASH_MOD4) */ #endif :