version 1.196, 2006/10/13 17:15:27
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version 1.200, 2006/10/27 21:47:01
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Line 809 n = n1*n2;
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Line 809 n = n1*n2;
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/ ( n1 n2 -- n ) core slash |
/ ( n1 n2 -- n ) core slash |
n = n1/n2; |
n = n1/n2; |
if(FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) n--; |
if (CHECK_DIVISION_SW && n2 == 0) |
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throw(BALL_DIVZERO); |
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if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) |
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throw(BALL_RESULTRANGE); |
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if (FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) |
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n--; |
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: |
/mod nip ; |
/mod nip ; |
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mod ( n1 n2 -- n ) core |
mod ( n1 n2 -- n ) core |
n = n1%n2; |
n = n1%n2; |
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if (CHECK_DIVISION_SW && n2 == 0) |
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throw(BALL_DIVZERO); |
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if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) |
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throw(BALL_RESULTRANGE); |
if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) n += n2; |
if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) n += n2; |
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: |
/mod drop ; |
/mod drop ; |
Line 822 if(FLOORED_DIV && ((n1^n2) < 0) && n!=0)
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Line 831 if(FLOORED_DIV && ((n1^n2) < 0) && n!=0)
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/mod ( n1 n2 -- n3 n4 ) core slash_mod |
/mod ( n1 n2 -- n3 n4 ) core slash_mod |
n4 = n1/n2; |
n4 = n1/n2; |
n3 = n1%n2; /* !! is this correct? look into C standard! */ |
n3 = n1%n2; /* !! is this correct? look into C standard! */ |
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if (CHECK_DIVISION_SW && n2 == 0) |
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throw(BALL_DIVZERO); |
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if (CHECK_DIVISION_SW && n2 == -1 && n1 == CELL_MIN) |
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throw(BALL_RESULTRANGE); |
if (FLOORED_DIV && ((n1^n2) < 0) && n3!=0) { |
if (FLOORED_DIV && ((n1^n2) < 0) && n3!=0) { |
n4--; |
n4--; |
n3+=n2; |
n3+=n2; |
Line 842 n4=DHI(r);
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Line 855 n4=DHI(r);
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n5=DLO(r); |
n5=DLO(r); |
#else |
#else |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n5 = d/n3; |
DCell d5 = d/n3; |
n4 = d%n3; |
n4 = d%n3; |
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if (CHECK_DIVISION_SW && n3 == 0) |
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throw(BALL_DIVZERO); |
if (FLOORED_DIV && ((DHI(d)^n3)<0) && n4!=0) { |
if (FLOORED_DIV && ((DHI(d)^n3)<0) && n4!=0) { |
n5--; |
d5--; |
n4+=n3; |
n4+=n3; |
} |
} |
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n5 = d5; |
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if (CHECK_DIVISION && d5 != n5) |
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throw(BALL_RESULTRANGE); |
#endif |
#endif |
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>r m* r> fm/mod ; |
>r m* r> fm/mod ; |
Line 864 DCell r = fmdiv(d,n3);
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Line 882 DCell r = fmdiv(d,n3);
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n4=DLO(r); |
n4=DLO(r); |
#else |
#else |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n4 = d/n3; |
DCell d4 = d/n3; |
if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) n4--; |
if (CHECK_DIVISION_SW && n3 == 0) |
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throw(BALL_DIVZERO); |
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if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) |
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d4--; |
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n4 = d4; |
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if (CHECK_DIVISION && d4 != n4) |
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throw(BALL_RESULTRANGE); |
#endif |
#endif |
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*/mod nip ; |
*/mod nip ; |
Line 893 fm/mod ( d1 n1 -- n2 n3 ) core f_m_sla
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Line 917 fm/mod ( d1 n1 -- n2 n3 ) core f_m_sla
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#ifdef ASM_SM_SLASH_REM |
#ifdef ASM_SM_SLASH_REM |
ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
if (((DHI(d1)^n1)<0) && n2!=0) { |
if (((DHI(d1)^n1)<0) && n2!=0) { |
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if (CHECK_DIVISION && n3 == CELL_MIN) |
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throw(BALL_RESULTRANGE); |
n3--; |
n3--; |
n2+=n1; |
n2+=n1; |
} |
} |
Line 905 n3=DLO(r);
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Line 931 n3=DLO(r);
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#ifdef ASM_SM_SLASH_REM4 |
#ifdef ASM_SM_SLASH_REM4 |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
if (((DHI(d1)^n1)<0) && n2!=0) { |
if (((DHI(d1)^n1)<0) && n2!=0) { |
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if (CHECK_DIVISION && n3 == CELL_MIN) |
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throw(BALL_RESULTRANGE); |
n3--; |
n3--; |
n2+=n1; |
n2+=n1; |
} |
} |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n3 = d1/n1; |
DCell d3 = d1/n1; |
n2 = d1%n1; |
n2 = d1%n1; |
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if (CHECK_DIVISION_SW && n1 == 0) |
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throw(BALL_DIVZERO); |
/* note that this 1%-3>0 is optimized by the compiler */ |
/* note that this 1%-3>0 is optimized by the compiler */ |
if (1%-3>0 && ((DHI(d1)^n1)<0) && n2!=0) { |
if (1%-3>0 && ((DHI(d1)^n1)<0) && n2!=0) { |
n3--; |
d3--; |
n2+=n1; |
n2+=n1; |
} |
} |
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n3 = d3; |
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if (CHECK_DIVISION && d3 != n3) |
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throw(BALL_RESULTRANGE); |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif |
#endif |
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Line 940 n3=DLO(r);
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Line 973 n3=DLO(r);
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ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
#else /* !defined(ASM_SM_SLASH_REM4) */ |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n3 = d1/n1; |
DCell d3 = d1/n1; |
n2 = d1%n1; |
n2 = d1%n1; |
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if (CHECK_DIVISION_SW && n1 == 0) |
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throw(BALL_DIVZERO); |
/* note that this 1%-3<0 is optimized by the compiler */ |
/* note that this 1%-3<0 is optimized by the compiler */ |
if (1%-3<0 && ((DHI(d1)^n1)<0) && n2!=0) { |
if (1%-3<0 && ((DHI(d1)^n1)<0) && n2!=0) { |
n3++; |
d3++; |
n2-=n1; |
n2-=n1; |
} |
} |
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n3 = d3; |
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if (CHECK_DIVISION && d3 != n3) |
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throw(BALL_RESULTRANGE); |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif |
#endif |
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Line 996 u3=DLO(r);
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Line 1034 u3=DLO(r);
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#ifdef ASM_UM_SLASH_MOD4 |
#ifdef ASM_UM_SLASH_MOD4 |
ASM_UM_SLASH_MOD4(ud, u1, u2, u3); |
ASM_UM_SLASH_MOD4(ud, u1, u2, u3); |
#else /* !defined(ASM_UM_SLASH_MOD4) */ |
#else /* !defined(ASM_UM_SLASH_MOD4) */ |
u3 = ud/u1; |
UDCell ud3 = ud/u1; |
u2 = ud%u1; |
u2 = ud%u1; |
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if (CHECK_DIVISION_SW && u1 == 0) |
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throw(BALL_DIVZERO); |
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u3 = ud3; |
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if (CHECK_DIVISION && ud3 != u3) |
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throw(BALL_RESULTRANGE); |
#endif /* !defined(ASM_UM_SLASH_MOD4) */ |
#endif /* !defined(ASM_UM_SLASH_MOD4) */ |
#endif |
#endif |
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