### Diff for /gforth/prim between versions 1.166 and 1.169

version 1.166, 2005/01/28 21:32:19 version 1.169, 2005/02/01 10:29:00
Line 805  n = n1*n2; Line 805  n = n1*n2;

/       ( n1 n2 -- n )          core    slash  /       ( n1 n2 -- n )          core    slash
n = n1/n2;  n = n1/n2;
if(FLOORED_DIV && (n1 < 0) != (n2 < 0) && (n1%n2 != 0)) n--;  if(FLOORED_DIV && ((n1^n2) < 0) && (n1%n2 != 0)) n--;
:  :
/mod nip ;   /mod nip ;

mod     ( n1 n2 -- n )          core  mod     ( n1 n2 -- n )          core
n = n1%n2;  n = n1%n2;
if(FLOORED_DIV && (n1 < 0) != (n2 < 0) && n!=0) n += n2;  if(FLOORED_DIV && ((n1^n2) < 0) && n!=0) n += n2;
:  :
/mod drop ;   /mod drop ;

/mod    ( n1 n2 -- n3 n4 )              core            slash_mod  /mod    ( n1 n2 -- n3 n4 )              core            slash_mod
n4 = n1/n2;  n4 = n1/n2;
n3 = n1%n2; /* !! is this correct? look into C standard! */  n3 = n1%n2; /* !! is this correct? look into C standard! */
if (FLOORED_DIV && (n1<0) != (n2<0) && n3!=0) {  if (FLOORED_DIV && ((n1^n2) < 0) && n3!=0) {
n4--;    n4--;
n3+=n2;    n3+=n2;
}  }
Line 840  n5=DLO(r); Line 840  n5=DLO(r);
/* assumes that the processor uses either floored or symmetric division */  /* assumes that the processor uses either floored or symmetric division */
n5 = d/n3;  n5 = d/n3;
n4 = d%n3;  n4 = d%n3;
if (FLOORED_DIV && (d<0) != (n3<0) && n4!=0) {  if (FLOORED_DIV && ((DHI(d)^n3)<0) && n4!=0) {
n5--;    n5--;
n4+=n3;    n4+=n3;
}  }
Line 857  DCell d = (DCell)n1 * (DCell)n2; Line 857  DCell d = (DCell)n1 * (DCell)n2;
#endif  #endif
#ifdef BUGGY_LL_DIV  #ifdef BUGGY_LL_DIV
DCell r = fmdiv(d,n3);  DCell r = fmdiv(d,n3);
n4=DHI(r);  n4=DLO(r);
#else  #else
/* assumes that the processor uses either floored or symmetric division */  /* assumes that the processor uses either floored or symmetric division */
n4 = d/n3;  n4 = d/n3;
if (FLOORED_DIV && (d<0) != (n3<0) && (d%n3)!=0) n4--;  if (FLOORED_DIV && ((DHI(d)^n3)<0) && (d%n3)!=0) n4--;
#endif  #endif
:  :
*/mod nip ;   */mod nip ;
Line 888  fm/mod ( d1 n1 -- n2 n3 )  core  f_m_sla Line 888  fm/mod ( d1 n1 -- n2 n3 )  core  f_m_sla
#ifdef BUGGY_LL_DIV  #ifdef BUGGY_LL_DIV
#ifdef ASM_SM_SLASH_REM  #ifdef ASM_SM_SLASH_REM
ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3);  ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3);
if ((d1.hi<0) != (n1<0) && n2!=0) {  if (((DHI(d1)^n1)<0) && n2!=0) {
n3--;    n3--;
n2+=n1;    n2+=n1;
}  }
Line 900  n3=DLO(r); Line 900  n3=DLO(r);
#else  #else
#ifdef ASM_SM_SLASH_REM4  #ifdef ASM_SM_SLASH_REM4
ASM_SM_SLASH_REM4(d1, n1, n2, n3);  ASM_SM_SLASH_REM4(d1, n1, n2, n3);
if ((d1<0) != (n1<0) && n2!=0) {  if (((DHI(d1)^n1)<0) && n2!=0) {
n3--;    n3--;
n2+=n1;    n2+=n1;
}  }
Line 909  if ((d1<0) != (n1<0) && n2!=0) { Line 909  if ((d1<0) != (n1<0) && n2!=0) {
n3 = d1/n1;  n3 = d1/n1;
n2 = d1%n1;  n2 = d1%n1;
/* note that this 1%-3>0 is optimized by the compiler */  /* note that this 1%-3>0 is optimized by the compiler */
if (1%-3>0 && (d1<0) != (n1<0) && n2!=0) {  if (1%-3>0 && ((DHI(d1)^n1)<0) && n2!=0) {
n3--;    n3--;
n2+=n1;    n2+=n1;
}  }
Line 939  ASM_SM_SLASH_REM4(d1, n1, n2, n3); Line 939  ASM_SM_SLASH_REM4(d1, n1, n2, n3);
n3 = d1/n1;  n3 = d1/n1;
n2 = d1%n1;  n2 = d1%n1;
/* note that this 1%-3<0 is optimized by the compiler */  /* note that this 1%-3<0 is optimized by the compiler */
if (1%-3<0 && (d1<0) != (n1<0) && n2!=0) {  if (1%-3<0 && ((DHI(d1)^n1)<0) && n2!=0) {
n3++;    n3++;
n2-=n1;    n2-=n1;
}  }
Line 990  u3=DLO(r); Line 990  u3=DLO(r);
#endif /* !defined(ASM_UM_SLASH_MOD) */  #endif /* !defined(ASM_UM_SLASH_MOD) */
#else  #else
#ifdef ASM_UM_SLASH_MOD4  #ifdef ASM_UM_SLASH_MOD4
ASM_UM_SLASH_MOD4(d1, n1, n2, n3);  ASM_UM_SLASH_MOD4(ud, u1, u2, u3);
#else /* !defined(ASM_UM_SLASH_MOD4) */  #else /* !defined(ASM_UM_SLASH_MOD4) */
u3 = ud/u1;  u3 = ud/u1;
u2 = ud%u1;  u2 = ud%u1;

 Removed from v.1.166 changed lines Added in v.1.169

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