version 1.166, 2005/01/28 21:32:19
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version 1.168, 2005/01/29 13:31:51
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Line 857 DCell d = (DCell)n1 * (DCell)n2;
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Line 857 DCell d = (DCell)n1 * (DCell)n2;
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#endif |
#endif |
#ifdef BUGGY_LL_DIV |
#ifdef BUGGY_LL_DIV |
DCell r = fmdiv(d,n3); |
DCell r = fmdiv(d,n3); |
n4=DHI(r); |
n4=DLO(r); |
#else |
#else |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n4 = d/n3; |
n4 = d/n3; |
Line 990 u3=DLO(r);
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Line 990 u3=DLO(r);
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#endif /* !defined(ASM_UM_SLASH_MOD) */ |
#endif /* !defined(ASM_UM_SLASH_MOD) */ |
#else |
#else |
#ifdef ASM_UM_SLASH_MOD4 |
#ifdef ASM_UM_SLASH_MOD4 |
ASM_UM_SLASH_MOD4(d1, n1, n2, n3); |
ASM_UM_SLASH_MOD4(ud, u1, u2, u3); |
#else /* !defined(ASM_UM_SLASH_MOD4) */ |
#else /* !defined(ASM_UM_SLASH_MOD4) */ |
u3 = ud/u1; |
u3 = ud/u1; |
u2 = ud%u1; |
u2 = ud%u1; |