--- gforth/prim	2005/01/26 22:06:03	1.164
+++ gforth/prim	2005/01/28 20:38:42	1.165
@@ -886,9 +886,17 @@ n2 = n1>>1;
 fm/mod	( d1 n1 -- n2 n3 )		core		f_m_slash_mod
 ""Floored division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, @i{n1}>@i{n2}>=0 or 0>=@i{n2}>@i{n1}.""
 #ifdef BUGGY_LL_DIV
+#ifdef ASM_SM_SLASH_REM
+ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3);
+if ((d1.hi<0) != (n1<0) && n2!=0) {
+  n3--;
+  n2+=n1;
+}
+#else /* !defined(ASM_SM_SLASH_REM) */
 DCell r = fmdiv(d1,n1);
 n2=DHI(r);
 n3=DLO(r);
+#endif /* !defined(ASM_SM_SLASH_REM) */
 #else
 /* assumes that the processor uses either floored or symmetric division */
 n3 = d1/n1;
@@ -908,9 +916,13 @@ if (1%-3>0 && (d1<0) != (n1<0) && n2!=0)
 sm/rem	( d1 n1 -- n2 n3 )		core		s_m_slash_rem
 ""Symmetric division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, sign(@i{n2})=sign(@i{d1}) or 0.""
 #ifdef BUGGY_LL_DIV
+#ifdef ASM_SM_SLASH_REM
+ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3);
+#else /* !defined(ASM_SM_SLASH_REM) */
 DCell r = smdiv(d1,n1);
 n2=DHI(r);
 n3=DLO(r);
+#endif /* !defined(ASM_SM_SLASH_REM) */
 #else
 /* assumes that the processor uses either floored or symmetric division */
 n3 = d1/n1;
@@ -957,9 +969,13 @@ ud = (UDCell)u1 * (UDCell)u2;
 um/mod	( ud u1 -- u2 u3 )		core	u_m_slash_mod
 ""ud=u3*u1+u2, u1>u2>=0""
 #ifdef BUGGY_LL_DIV
+#ifdef ASM_UM_SLASH_MOD
+ASM_UM_SLASH_MOD(ud.lo, ud.hi, u1, u2, u3);
+#else /* !defined(ASM_UM_SLASH_MOD) */
 UDCell r = umdiv(ud,u1);
 u2=DHI(r);
 u3=DLO(r);
+#endif /* !defined(ASM_UM_SLASH_MOD) */
 #else
 u3 = ud/u1;
 u2 = ud%u1;