version 1.164, 2005/01/26 22:06:03
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version 1.167, 2005/01/28 21:36:45
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Line 886 n2 = n1>>1;
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Line 886 n2 = n1>>1;
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fm/mod ( d1 n1 -- n2 n3 ) core f_m_slash_mod |
fm/mod ( d1 n1 -- n2 n3 ) core f_m_slash_mod |
""Floored division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, @i{n1}>@i{n2}>=0 or 0>=@i{n2}>@i{n1}."" |
""Floored division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, @i{n1}>@i{n2}>=0 or 0>=@i{n2}>@i{n1}."" |
#ifdef BUGGY_LL_DIV |
#ifdef BUGGY_LL_DIV |
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#ifdef ASM_SM_SLASH_REM |
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ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
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if ((d1.hi<0) != (n1<0) && n2!=0) { |
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n3--; |
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n2+=n1; |
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} |
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#else /* !defined(ASM_SM_SLASH_REM) */ |
DCell r = fmdiv(d1,n1); |
DCell r = fmdiv(d1,n1); |
n2=DHI(r); |
n2=DHI(r); |
n3=DLO(r); |
n3=DLO(r); |
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#endif /* !defined(ASM_SM_SLASH_REM) */ |
#else |
#else |
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#ifdef ASM_SM_SLASH_REM4 |
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ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
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if ((d1<0) != (n1<0) && n2!=0) { |
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n3--; |
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n2+=n1; |
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} |
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#else /* !defined(ASM_SM_SLASH_REM4) */ |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n3 = d1/n1; |
n3 = d1/n1; |
n2 = d1%n1; |
n2 = d1%n1; |
Line 898 if (1%-3>0 && (d1<0) != (n1<0) && n2!=0)
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Line 913 if (1%-3>0 && (d1<0) != (n1<0) && n2!=0)
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n3--; |
n3--; |
n2+=n1; |
n2+=n1; |
} |
} |
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#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif |
#endif |
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dup >r dup 0< IF negate >r dnegate r> THEN |
dup >r dup 0< IF negate >r dnegate r> THEN |
Line 908 if (1%-3>0 && (d1<0) != (n1<0) && n2!=0)
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Line 924 if (1%-3>0 && (d1<0) != (n1<0) && n2!=0)
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sm/rem ( d1 n1 -- n2 n3 ) core s_m_slash_rem |
sm/rem ( d1 n1 -- n2 n3 ) core s_m_slash_rem |
""Symmetric division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, sign(@i{n2})=sign(@i{d1}) or 0."" |
""Symmetric division: @i{d1} = @i{n3}*@i{n1}+@i{n2}, sign(@i{n2})=sign(@i{d1}) or 0."" |
#ifdef BUGGY_LL_DIV |
#ifdef BUGGY_LL_DIV |
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#ifdef ASM_SM_SLASH_REM |
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ASM_SM_SLASH_REM(d1.lo, d1.hi, n1, n2, n3); |
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#else /* !defined(ASM_SM_SLASH_REM) */ |
DCell r = smdiv(d1,n1); |
DCell r = smdiv(d1,n1); |
n2=DHI(r); |
n2=DHI(r); |
n3=DLO(r); |
n3=DLO(r); |
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#endif /* !defined(ASM_SM_SLASH_REM) */ |
#else |
#else |
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#ifdef ASM_SM_SLASH_REM4 |
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ASM_SM_SLASH_REM4(d1, n1, n2, n3); |
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#else /* !defined(ASM_SM_SLASH_REM4) */ |
/* assumes that the processor uses either floored or symmetric division */ |
/* assumes that the processor uses either floored or symmetric division */ |
n3 = d1/n1; |
n3 = d1/n1; |
n2 = d1%n1; |
n2 = d1%n1; |
Line 920 if (1%-3<0 && (d1<0) != (n1<0) && n2!=0)
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Line 943 if (1%-3<0 && (d1<0) != (n1<0) && n2!=0)
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n3++; |
n3++; |
n2-=n1; |
n2-=n1; |
} |
} |
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#endif /* !defined(ASM_SM_SLASH_REM4) */ |
#endif |
#endif |
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over >r dup >r abs -rot |
over >r dup >r abs -rot |
Line 957 ud = (UDCell)u1 * (UDCell)u2;
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Line 981 ud = (UDCell)u1 * (UDCell)u2;
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um/mod ( ud u1 -- u2 u3 ) core u_m_slash_mod |
um/mod ( ud u1 -- u2 u3 ) core u_m_slash_mod |
""ud=u3*u1+u2, u1>u2>=0"" |
""ud=u3*u1+u2, u1>u2>=0"" |
#ifdef BUGGY_LL_DIV |
#ifdef BUGGY_LL_DIV |
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#ifdef ASM_UM_SLASH_MOD |
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ASM_UM_SLASH_MOD(ud.lo, ud.hi, u1, u2, u3); |
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#else /* !defined(ASM_UM_SLASH_MOD) */ |
UDCell r = umdiv(ud,u1); |
UDCell r = umdiv(ud,u1); |
u2=DHI(r); |
u2=DHI(r); |
u3=DLO(r); |
u3=DLO(r); |
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#endif /* !defined(ASM_UM_SLASH_MOD) */ |
#else |
#else |
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#ifdef ASM_UM_SLASH_MOD4 |
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ASM_UM_SLASH_MOD4(ud, u1, u2, u3); |
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#else /* !defined(ASM_UM_SLASH_MOD4) */ |
u3 = ud/u1; |
u3 = ud/u1; |
u2 = ud%u1; |
u2 = ud%u1; |
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#endif /* !defined(ASM_UM_SLASH_MOD4) */ |
#endif |
#endif |
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0 swap [ 8 cells 1 + ] literal 0 |
0 swap [ 8 cells 1 + ] literal 0 |