--- gforth/prim	2003/09/14 21:16:48	1.144
+++ gforth/prim	2003/10/09 20:25:59	1.146
@@ -136,6 +136,47 @@
 \ throw execute, cfa and NEXT1 out?
 \ macroize *ip, ip++, *ip++ (pipelining)?
 
+\ Stack caching setup
+
+\E register IPTOS Cell
+\E register spa Cell
+\E register spb Cell
+\E register spc Cell
+\E register spd Cell
+
+\E create IPregs IPTOS ,
+\E create regs spc , spb , spa ,
+
+\E IPregs 1 0 stack-state IPss1
+\E regs 3 cells + 0 0 stack-state ss0
+\E regs 2 cells + 1  0 stack-state ss1
+\E regs 1 cells + 2  1 stack-state ss2
+\E regs 0 cells + 3  2 stack-state ss3
+
+\ the first of these is the default state
+\E state S0
+\E state S1
+\E state S2
+\E state S3
+
+\E ss0 data-stack S0 set-ss
+\E ss1 data-stack S1 set-ss
+\E ss2 data-stack S2 set-ss
+\E ss3 data-stack S3 set-ss
+
+\E IPss1 inst-stream S0 set-ss
+\E IPss1 inst-stream S1 set-ss
+\E IPss1 inst-stream S2 set-ss
+\E IPss1 inst-stream S3 set-ss
+
+\E data-stack to cache-stack
+\E here 4 cache-states 2! s0 , s1 , s2 , s3 ,
+
+\ !! the following should be automatic
+\E S0 to state-default
+\E state-default to state-in
+\E state-default to state-out
+
 \ these m4 macros would collide with identifiers
 undefine(`index')
 undefine(`shift')