Liste der Diplomarbeiten

Betreut von Andreas Krall (andi@complang.tuwien.ac.at, Tel. 58801/18511)

Diplomarbeiten

1. Diplomarbeit: Architecture Emulator Generator (bezahlt)
Im Rahmen dieser Diplomarbeit soll ein Generator für zyklengenaue Architektur Emulatoren entwickelt werden. Die Architekturen werden in einer ADL beschrieben. Der Emulator soll Übersetzung und Interpretation unterstützen.
2. Diplomarbeit: Tree Pattern Matcher based on lburg
The CDLab (Christian Doppler Labor) 'Compilation Techniques for Embedded Processors' currently develops a compiler for the CHILI architecture by OnDemand Microelectronics.

The CHILI is a four-way VLIW DSP (Digital Signal Processor) designed for efficient processing of video/audio streams. The architecture offers an extensive general purpose register file, with 64 32 bit registers. A distinguishing feature of the CHILI is it's capability to execute most instructions conditionally and it's memory subsystem. The CHILI is able to execute up to four load and store instructions concurrently.

The compiler is based on the LLVM compiler infrastructure developed at the University of Illinois. LLVM is a C++ based framework for static compilers, dynamic compilers (Just-In-Time, JIT), (whole) program optimizations and (whole) program analysis.

The instruction selector of the LLVM infrastructure is based on a simple buttom-up DAG matcher. This work should implement a two-pass instruction selector based on dynamic programming, well known from systems like lburg[1]. Patterns for the tree grammer should be derived using the `tablegen` tool included in LLVM.

- Prerequisites:
* Good knowledge of C++
* Basic compiler courses
- [1] Christopher W. Fraser and David R. Hanson and Todd A. Proebsting, "Engineering a simple, efficient code-generator generator", 1992, p. 213-126, ACM Letters on Programming Languages and Systems

3. Diplomarbeit: Compiler for arm-processor
Context YesControl is a DCS-System, consisting of a SCADA (Supervisory Control and Data Acquisition) system and a PLC (programmable logic control) based on IEC 61131-3. Its concept of combining these two worlds with one engineering tool based on standard hardware for SCADA and PLC is unique, and the integration is much better than competitive products on the market. Task Description YesControl has an integrated compiler, which compiles Structured-Text- Source to Intel X86 assembler code, which then runs on the PLC. The Compiler first generates intermediate code, and then the intermediate code is compiled by the backend to the assembler code of the corresponding processor, with the help of The New Jersey Machine-Code Toolkit (see http://www.eecs.harvard.edu/~nr/toolkit/) The task of this diploma thesis is to port the PLC runtime system of YesControl (which is easily portable plain C) to an arm-processor-based hardware, and then to make an arm-backend for the compiler, including a Dissassembler for the ARM built with the help of the New Jersey machine- Code Toolkit Requirements
. Good knowledge in C
. Interest in building compilers
. knowledge of the arm-processor would be helpful, but is not necessary
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