The speedup we saw for our LaTeX benchmark was 5%; and the difference is also visible in the lmbench results.
I was worried about cache consistency issues arising with the virtually indexed cache. Therefore I have written a test program for checking this. The result is that the test went well even with 16K D-cache. My guess is that the hardware invalidates the other cached instance of the same physical memory location automatically with bus snooping logic or somesuch.
This module has been tested successfully on a Cabriolet booted with ARC and MILO. The latest version of this module reportedly fixes the problems that have been reported for the Avanti. It probably won't work if you boot with SRM without MILO (but it's probably not necessary then). Please report any positive and negative experiences to email@example.com.