The Case for Virtual Register Machines

Brian Davis, Andrew Beatty, David Gregg and John Waldron

Workshop on Interpreters, Virtual Machines and Emulators (IVME03), San Diego, California, 12 Jun 2003


Abstract

Virtual machines (VMs) are a popular target for language implementers. Conventional wisdom tells us that virtual stack architectures can be implemented with an interpreter more efficiently, since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduces the number of executed instructions by over 35\%, suggesting that virtual register machines are a viable alternative to stack machines when interpreted on modern pipelined architectures.


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